Storage Apparatus Sequential Learning for Access Pattern Response
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Solution Overview
Problem
Conventional storage apparatuses with a multi microprocessor configuration struggle to perform efficient sequential learning due to limited data retention capacity and delayed recognition of sequential access patterns, restricting the range of observable access patterns and hindering response performance for various access patterns.
Innovation Solution
A storage apparatus with a processor that shares learning results across microprocessors, performs sequential learning in units of blocks and slots, and expands the data range based on learning results, enabling efficient staging and prefetching for various access patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If sequential learning is performed only based on logical block address continuity in multi-microprocessor configurations, then each microprocessor can independently learn access patterns, but the range of observable access patterns is limited and recognition of sequential access is delayed
Solution Approach 1:
The patent merges the sequential learning functions of multiple microprocessors into a unified learning system. The management microprocessor consolidates access pattern information from all data processing microprocessors, enabling broader observation of access patterns across the entire storage apparatus rather than limiting learning to individual microprocessor perspectives.
Solution Approach 2:
The management microprocessor acts as an intermediary that collects, processes, and integrates access pattern information from multiple data processing microprocessors. This intermediary role enables the system to observe a wider range of access patterns and make more accurate sequential learning decisions that benefit the entire system.
2Speed
If data is staged in advance for sequential access patterns, then response performance improves, but memory capacity is consumed for retaining learning information
Solution Approach 1:
The patent implements local quality by having each data processing microprocessor maintain learning information only for its locally processed data, while the management microprocessor maintains overall access patterns. This distributed approach reduces the memory burden on individual components while preserving the ability to improve response performance through selective prefetching.
Solution Approach 2:
The system performs partial prefetching by staging only the portion of data that is predicted to be accessed next, rather than prefetching entire data sets. This partial action approach improves response performance for predicted access patterns while consuming minimal memory capacity for learning information.
3Quantity of substance
If each microprocessor retains learning results independently, then data retention capacity is reduced, but recognition of sequential access patterns is delayed
Solution Approach 1:
The patent merges learning results from multiple microprocessors into a unified knowledge base managed by the management microprocessor. This consolidation allows the system to recognize sequential access patterns more quickly by aggregating observations from all microprocessors rather than waiting for individual microprocessors to independently discover patterns.
Solution Approach 2:
The system implements feedback mechanisms where the management microprocessor continuously receives access pattern information from data processing microprocessors and uses this feedback to refine sequential learning decisions. This real-time feedback loop reduces the time required to recognize and respond to sequential access patterns.
Data Source
AI summary
Proposed are a storage apparatus and a control method thereof capable of improving the response performance to a read access of various access patterns. When data to be read is not retained in a data buffer memory, upon staging the data to be read, a processor performs sequential learning of respectively observing an access pattern in units of blocks of a predetermined size and an access pattern in units of slots configured from a plurality of the blocks regarding an access pattern of the read access from the host apparatus, and expands a data range to be staged as needed based on a learning result of the sequential learning.