Storage Server Channel Assignment for Write Amplification

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Solution Overview

Problem

Conventional RAID systems with Solid State Drives (SSDs) experience high write amplification index (WAI), leading to inefficient storage operations, especially in all-flash array storage servers, due to complex flash memory management and high operational overhead.

Innovation Solution

Implementing a method where multiple channels within a storage server's memory devices are assigned for access control corresponding to threads, allowing for sequential writing of logical access units into a RAID configuration, using a memory controller to manage NV memory elements across these channels, thereby reducing WAI and enhancing storage performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional RAID is implemented with SSDs, then data protection and storage functionality are achieved, but write amplification index becomes high

Engineering Contradiction:
Improvedata protectionVSAvoidwrite amplification index
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The invention divides the flash memory device into multiple channels, with each channel independently managing specific data sets. This segmentation allows parallel write operations across channels, reducing the need for sequential read-modify-write cycles and thereby lowering write amplification while maintaining data protection through distributed parity management.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system pre-allocates specific channels for data sets and configures parity management before write operations occur. By establishing channel assignments and parity structures in advance, the system avoids complex real-time decision-making during writes, reducing write amplification while ensuring data protection is maintained through pre-planned redundancy distribution.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If flash memory management is implemented to protect multiple data sets, then data reliability is improved, but operational complexity increases

Engineering Contradiction:
Improvedata set protectionVSAvoidflash memory management
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

By dividing flash memory into multiple independent channels, each managing specific data sets and parity information, the system simplifies management complexity. Each channel operates semi-independently with dedicated buffers and controllers, transforming a complex monolithic management system into simpler modular units that can be managed in parallel.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention introduces channel-specific buffers as intermediary structures between the controller and flash memory channels. These buffers manage data staging and parity calculation locally within each channel, reducing the burden on the central controller and simplifying overall management while maintaining robust multi-data-set protection.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If sequential write operations are performed across memory devices, then data integrity is maintained, but write efficiency decreases

Engineering Contradiction:
Improvedata integrityVSAvoidwrite efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The system segments write operations across multiple independent channels, allowing simultaneous write operations to proceed in parallel. Each channel maintains data integrity independently through its own buffer and controller, enabling overall system write efficiency to improve while preserving data integrity through distributed parallel processing.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

By maintaining dedicated buffers and continuous write capabilities in each channel, the system eliminates idle periods between sequential writes. Multiple channels can continuously perform write operations simultaneously, ensuring that useful write actions continue without interruption across the system while maintaining data integrity through parallel independent operations.

Inventive Principle:
Principle #20Continuity of useful action

Data Source

PatentUS11366616B2Method for performing storage control in a storage server, associated memory device and memory controller thereof, and associated storage server
Publication Date: 2022.06.21 SILICON MOTION INC
  • US11366616B2 patent drawing
  • US11366616B2 patent drawing
  • US11366616B2 patent drawing

AI summary

A method for performing storage control in a storage server may include: regarding any memory device of a plurality of memory devices installed at the storage server, assigning a channel of multiple channels within the memory device for access control corresponding to a thread of a plurality of threads running on the storage server, wherein the storage server configures the plurality of memory devices to form a RAID of the storage server; and during storing a series of logical access units (LAUs) into the RAID, writing information into respective sets of pages of the plurality of memory devices as pages in a LAU of the series of LAUs according to a predetermined arrangement rule, to make the respective sets of pages be sequentially written into the plurality of memory devices respectively with aid of the assignment of the channel of the multiple channels to the thread. Associated apparatus are provided.