Storage Switch Error Injection for NVMe I/O Path Testing
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Solution Overview
Problem
The increasing stability and reliability requirements of PCIe bus systems in the storage industry, particularly for next-generation NVMe disks, are not adequately addressed by existing methods for testing error handling capabilities, as manufacturers lack a method to directly inject and simulate errors across the entire I/O path from storage devices to computing devices.
Innovation Solution
A method is introduced where information representing errors is injected into a switch of a storage system, passed from an upstream port to a computing device, and analyzed to determine the error handling capability of the system, allowing comprehensive testing of error processing without requiring dedicated error injection tools.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional error testing methods are used, then error handling capability can be tested, but the testing cannot cover the entire I/O path from storage devices to computing devices
Solution Approach 1:
The patent introduces a switch as an intermediary component in the error injection path. The switch receives error injection commands from the testing device, forwards them to the target storage device through the PCIe bus, and returns the responses. This intermediary enables comprehensive testing of the entire I/O path including the PCIe bus and switch itself, which cannot be achieved by direct connection testing methods.
2Reliability
If dedicated error injection tools are used, then error injection capability is improved, but device complexity and cost increase
Solution Approach 1:
The switch serves multiple functions: it acts as a routing device for normal data traffic, an error injection intermediary for testing, and a testable component itself. By leveraging the existing switch infrastructure already present in NVMe storage systems, the patent eliminates the need for dedicated error injection tools, reducing device complexity and cost while maintaining comprehensive testing capability.
Solution Approach 2:
The storage system's own switch is utilized to perform error injection testing on the system itself. The switch that is already part of the NVMe architecture is repurposed as the error injection intermediary, allowing the system to test its own error handling capabilities without requiring external specialized equipment.
Data Source
AI summary
Techniques for error detection involve injecting, to a switch of a storage system, information representing an error of at least one device to be tested of the system, such that the information representing the error is passed from an upstream port of the switch to a computing device connected with the switch, the switch being connected to the at least one device to be tested via a downstream port. The techniques further involve obtaining a handling result of the computing device on the information representing the error, and determining an error handling capability of the system at least partly by analyzing the handling result. Accordingly, slave storage devices of storage system nodes, connectors, the entire PCIe topology at the CPU level, and an NVMe bus can be tested, so that the entire logical path of the error handling can be tested, thereby improving performance and saving testing costs.