Storage Switch Unit Segmentation for Mainframe Mirroring Throughput

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Solution Overview

Problem

Current data storage systems face challenges in supporting multiple host interface types, leading to throughput bottlenecks and slow response times, particularly when handling mainframe hosts requiring high throughput and open system hosts with varying protocols and throughputs, while also struggling with scalability and redundancy.

Innovation Solution

A data storage system with multiple control modules, channel adaptors, and switch units that selectively switch connections between control modules and adaptors, utilizing high-speed serial buses and multiple switch units to manage cache memory and access memory devices efficiently, supporting different host protocols and throughputs, and ensuring redundancy and scalability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a single router is used to interconnect control managers, channel adaptors, and disk adaptors, then the device complexity is reduced, but the throughput becomes bottlenecked and response time increases

Engineering Contradiction:
Improvedevice complexityVSAvoidthroughput
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent divides the single router into multiple routers (first router and second router). The first router handles communications between control managers and channel adaptors, while the second router handles communications between control managers and disk adaptors. This segmentation eliminates the throughput bottleneck by distributing traffic across multiple dedicated paths, while keeping each router's individual complexity manageable.

Inventive Principle:
Principle #1Segmentation

2Adaptability or versatility

If multiple host interface types are supported in a single storage system, then the adaptability is improved, but the response time slows down due to protocol conversion overhead

Engineering Contradiction:
ImproveadaptabilityVSAvoidresponse time
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent introduces control managers as intermediary components between different host interface types (channel adaptors for mainframe hosts and disk adaptors for open system hosts). Each control manager runs multiple operating systems that can handle different protocols, acting as a mediator that translates between protocol requirements without adding significant overhead, thus maintaining fast response times while supporting multiple interface types.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If redundancy is implemented by interconnecting control managers through routers, then the reliability is improved, but the device complexity increases

Engineering Contradiction:
ImprovereliabilityVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent makes each control manager multi-functional by equipping it with both channel adaptor capabilities (for mainframe host interfaces) and disk adaptor capabilities (for open system host interfaces). This universality allows control managers to directly handle different protocol types without requiring additional dedicated components for each protocol, reducing overall device complexity while maintaining redundancy through the router interconnections.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS7418533B2Data storage system and control apparatus with a switch unit connected to a plurality of first channel adapter and modules wherein mirroring is performed
Publication Date: 2008.08.26 FUJITSU LTD
  • US7418533B2 patent drawing
  • US7418533B2 patent drawing
  • US7418533B2 patent drawing

AI summary

A storage system has a plurality of control modules for controlling a storage device for accesses from a mainframe host and an open system host respectively supporting different protocols. An open channel adaptor and a mainframe channel adaptor are separately provided. The mainframe channel adaptor is connected to a plurality of control managers via front routers and performs parallel write access from the mainframe host for mirroring. In the write processing for the mainframe host, the connection is maintained until the completion of processing. In particular, even in case of a write miss, disk read processing can be performed in parallel, thus contributing to the high-speed processing in case of the write miss. Further, for an access from the open system host, a high throughput can be obtained.