Storage System Processor Failover via Protocol Chip Address Translation
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Solution Overview
Problem
Current storage systems face challenges in maintaining continuous IO communication with a host apparatus when a processor of a storage controller fails, as existing solutions require complex control units like local routers or NTBs, which can fail or require restarts during OS updates, leading to temporary system downtime.
Innovation Solution
A storage system configuration with multiple protocol chips and processors, utilizing address translation units to seamlessly transfer IO requests and responses between processors, ensuring continuous operation even when one processor stops, without the need for specialized control units like local routers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a local router is introduced to automatically switch IO communication when a processor stops, then system reliability is improved, but device complexity increases and the local router itself may fail or require restarts during OS updates
Solution Approach 1:
The patent removes the local router component from the system and extracts its functionality to be implemented directly in the protocol chip. This eliminates the complexity of having a separate control unit while maintaining the automatic switching capability. The protocol chip directly manages address translation and request routing without needing an additional router component.
Solution Approach 2:
The protocol chip is designed to perform multiple functions: it handles protocol control for IO communication with the host apparatus, performs address translation between different address spaces, and automatically routes requests to appropriate processors. This multi-functionality eliminates the need for separate specialized components like local routers.
2Adaptability or versatility
If NTBs are used for address translation between processors, then address management is improved, but the system requires complex control and specialized hardware components
Solution Approach 1:
The patent merges the address translation function with the protocol chip, combining what were previously separate functions (protocol control and address translation) into a single integrated component. This eliminates the need for separate NTB hardware and simplifies the overall system architecture while maintaining address management capabilities.
Solution Approach 2:
The protocol chip performs address translation autonomously without requiring external control from a local router or other specialized components. The address translation is integrated into the protocol chip's operation, allowing it to self-manage the translation process as part of its normal function.
3Device complexity
If only one NTB is installed per controller with protocol chips using processor-controlled addresses, then device complexity is reduced, but automatic request routing fails when a processor stops
Solution Approach 1:
The patent implements dynamic address translation where the protocol chip can adaptively select which processor to route requests to based on the operational status of processors. The address translation mechanism is dynamic rather than static, allowing it to respond to processor failures and redistribute requests accordingly.
Solution Approach 2:
The system incorporates feedback mechanisms where the protocol chip monitors processor status and uses this information to adjust request routing. When a processor stops, the protocol chip receives feedback about this state change and automatically modifies its behavior to route requests to available processors.
Data Source
AI summary
A protocol chip transmits the request from the host apparatus to a first processor through a first address translation unit. A first processor transmits a response to the request from the host apparatus, to the protocol chip through the first address translation unit. When the first processor stops processing, an instruction to transmit the request from the host apparatus to a second processor is transmitted to the protocol chip. When receiving the instruction to transmit the request from the host apparatus to the second processor, the protocol chip transmits the request from the host apparatus to the second processor through a second address translation unit. The second processor transmits the response to the request from the host apparatus to the protocol chip through the second address translation unit.