Storage System Local Memory Cache for Control Information

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Solution Overview

Problem

In storage systems with multiple processors, accessing shared memory results in longer latency compared to local memory, reducing system performance, especially when the number of accesses increases, and requiring multiple local memories increases costs.

Innovation Solution

The storage system caches part of the control information in local memories on a type-by-type basis, improving the local memory hit probability by dividing control information into configuration-dependent and capacity-dependent types and optimizing cache management to prevent frequent access to shared memory.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If control information is stored in shared memory, then system reliability is improved through centralized management, but access latency increases reducing processing performance

Engineering Contradiction:
Improvesystem reliabilityVSAvoidaccess latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The control information is segmented into different types (configuration-dependent and capacity-dependent) and cached in different storage areas of local memory. This segmentation allows frequently accessed control information to be stored locally, reducing access latency while maintaining the shared memory as the authoritative source for reliability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Local memory acts as an intermediary between the processor and shared memory. The control information cache in local memory serves as a mediator that provides fast access to frequently used control information, reducing the need for direct shared memory access and thereby reducing access latency while maintaining data consistency.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Loss of time

If whole control information is stored in local memories, then access latency is reduced improving processing performance, but memory requirements increase leading to higher costs

Engineering Contradiction:
Improveaccess latencyVSAvoidmemory requirements
Core Design Contradiction:
Loss of timeVSQuantity of substance

Solution Approach 1:

Different storage areas in local memory are allocated based on the access patterns and characteristics of different control information types. Configuration-dependent control information that is frequently accessed is cached in local memory, while capacity-dependent control information is kept in shared memory. This local quality approach optimizes memory usage by storing only necessary control information locally.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

Instead of caching all control information in local memory, only the necessary portion (configuration-dependent control information) is cached. This partial action approach reduces memory requirements while still achieving the goal of reducing access latency for frequently accessed control information.

Inventive Principle:
Principle #16Partial or excessive action

3Productivity

If multiple local memories are provided for each processor, then access performance is improved, but system cost increases

Engineering Contradiction:
Improveaccess performanceVSAvoidsystem cost
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The local memory is designed to serve multiple functions: storing configuration-dependent control information, caching frequently accessed data, and acting as a buffer between the processor and shared memory. This multi-functionality allows a single local memory to provide improved access performance without requiring multiple dedicated memory units, thereby reducing system cost.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS8656119B2Storage system, control program and storage system control method
Publication Date: 2014.02.18 HITACHI VANTARA LTD
  • US8656119B2 patent drawing
  • US8656119B2 patent drawing
  • US8656119B2 patent drawing

AI summary

There is provided a storage system including one or more LDEVs, one or more processors, a local memory or memories corresponding to the processor or processors, and a shared memory, which is shared by the processors, wherein control information on I/O processing or application processing is stored in the shared memory, and the processor caches a part of the control information in different storage areas on a type-by-type basis in the local memory or memories corresponding to the processor or processors in referring to the control information stored in the shared memory.