Storage Tiering Control Device Prevents Cross-Access Degradation

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Solution Overview

Problem

Automated storage tiering technologies face performance degradation due to direct and cross access issues when frequently accessed data units are transferred between storage tiers, particularly in scenarios where straight access rates and cache hit rates are high, leading to inefficiencies in data relocation.

Innovation Solution

A control device that collects and analyzes multiple types of performance information, including access frequency, straight access rate, and cache hit rate, to determine optimal tier transfers, ensuring data units are not immediately relocated to higher tiers when performance degradation is likely, thereby minimizing memory capacity requirements and maintaining system performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If data units with high access frequency are transferred to higher storage tiers, then response time is improved, but cross-access communications increase causing performance degradation

Engineering Contradiction:
Improveresponse timeVSAvoidsystem performance
Core Design Contradiction:
SpeedVSProductivity

Solution Approach 1:

The control device collects multiple performance indicators including access frequency, straight access rate, and cache hit rate to make transfer decisions. This feedback mechanism prevents premature transfers by considering the cache hit rate, which indicates whether the data is frequently accessed from cache rather than requiring disk transfers.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The system uses multiple performance parameters (access frequency, straight access rate, cache hit rate) instead of a single parameter to determine transfer timing. By changing from a simple access frequency threshold to a multi-parameter evaluation system, the patent avoids transferring data that would cause cross-access performance degradation.

Inventive Principle:
Principle #35Parameter changes

2Speed

If data units are transferred to higher storage tiers, then access speed is improved, but unnecessary transfers increase memory capacity requirements

Engineering Contradiction:
Improveaccess speedVSAvoidmemory capacity
Core Design Contradiction:
SpeedVSQuantity of substance

Solution Approach 1:

The control device monitors cache hit rate as a feedback parameter to determine whether data units should be transferred. When the cache hit rate is high, it indicates that data is being accessed frequently from cache memory, so transfer to higher tiers is postponed, reducing memory capacity requirements.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The system evaluates multiple parameters including cache hit rate before initiating transfers. This multi-parameter approach ensures that data is only transferred when necessary, optimizing the balance between access speed and memory capacity utilization.

Inventive Principle:
Principle #35Parameter changes

3Device complexity

If straightforward transfer policy is used, then implementation is simple, but performance degradation occurs due to increased cross-access communications

Engineering Contradiction:
Improvecontrol logicVSAvoidsystem performance
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The control device implements a feedback-based transfer decision system that collects multiple performance indicators. This feedback mechanism adds control logic but prevents performance degradation by avoiding premature transfers that would cause cross-access communications.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The system transitions from a simple single-parameter transfer policy to a multi-parameter evaluation system. This increases control logic complexity but resolves the performance degradation issue by considering cache hit rate and straight access rate in addition to access frequency.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS9904474B2Control device and storage system
Publication Date: 2018.02.27 FUJITSU LTD
  • US9904474B2 patent drawing
  • US9904474B2 patent drawing
  • US9904474B2 patent drawing

AI summary

A control device includes a processor. The processor is configured to collect plural types of performance information regarding a first data unit. The processor is configured to determine, on basis of the collected plural types of performance information, whether to transfer the first data unit from a first storage device which is under control of a first controller to a second storage device which is positioned as higher than the first storage device. The processor is configured to transfer the first data unit from the first storage device to the second storage device depending on a result of the determination.