Storage Device Trim Bitmap Segmentation for Mapping Speed
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Solution Overview
Problem
Current storage devices face inefficiencies in trim processing operations, leading to slower performance and longer response times when handling trim requests from hosts, due to the complexity of managing address mapping and trim bitmap information.
Innovation Solution
The implementation of a storage device with a memory controller that utilizes multiple trim bitmap information sets, each representing different groups of logical addresses, allowing for efficient mapping state changes based on the number of trim-requested addresses, thereby optimizing trim processing speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a single trim bitmap information structure is used to manage all logical addresses, then the device structure remains simple, but the trim processing operation speed decreases due to the complexity of managing large numbers of logical addresses
Solution Approach 1:
The patent divides the single trim bitmap information into multiple trim bitmap information sets, where each set manages a specific group of logical addresses. This segmentation allows the system to process smaller chunks of address mappings simultaneously, improving trim processing speed while keeping each individual bitmap set manageable in size and complexity.
2Productivity
If multiple trim bitmap information sets are used to represent different groups of logical addresses, then the trim processing speed improves, but the device structure becomes more complex
Solution Approach 1:
The patent introduces an address mapping management unit that acts as an intermediary between the host and multiple trim bitmap information sets. This intermediary automatically selects and manages the appropriate bitmap set based on the logical address group being processed, shielding the complexity from the host while enabling efficient parallel processing of multiple address groups.
3Loss of time
If all trim-requested logical addresses are processed at once in a single operation, then the response time is shorter, but the system becomes unstable when handling large numbers of addresses
Solution Approach 1:
The patent segments the processing of trim-requested logical addresses by dividing them into different address groups, each managed by a separate trim bitmap information set. This allows the system to process addresses in manageable batches rather than all at once, maintaining system stability while minimizing total response time through parallel batch processing.
Data Source
AI summary
The present technology relates to an electronic device. A storage device includes a memory device including pages, a buffer memory configured to store address mapping information including a mapping relationship between logical addresses provided from a host and physical addresses corresponding to the pages, first trim bitmap information including trim information of first logical address groups each including a first number of logical addresses having at least two of the logical addresses, and second trim bitmap information including trim information of second logical address groups each including a second number of logical addresses greater than the first number of the logical addresses, and a memory controller configured to change, based on a number of trim-requested logical addresses from the host, map states of the trim-requested logical addresses in one of the address mapping information, the first trim bitmap information, and the second trim bitmap information.