Storage Wafer Defective Chip Replacement via Vertical Stacking
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Solution Overview
Problem
The existing storage wafer manufacturing methods face challenges in maximizing the percentage of non-defective chips due to the inclusion of defective NAND chip units, which reduces the yield and efficiency of memory devices.
Innovation Solution
The method involves forming non-defective NAND chip units on a separate wafer and mounting them on top of defective units on an initial wafer, allowing the non-defective units to be accessed by probe electrodes, thereby increasing the usable non-defective chip count and maintaining the wafer's functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If defective NAND chip units are included on the wafer, then the wafer can be fully utilized with all units undergoing probing, but the percentage of non-defective chips decreases and manufacturing yield is reduced
Solution Approach 1:
The patent introduces a vertical stacking dimension by mounting a second wafer (containing replacement NAND chip units) onto the first wafer (containing defective NAND chip units). This multi-layer configuration allows probe electrodes to access replacement units through vias in the adhesive film, effectively transforming a two-dimensional wafer surface problem into a three-dimensional solution space.
Solution Approach 2:
The adhesive film serves as an intermediary structure that enables electrical connection between the probe electrodes and the replacement NAND chip units. By forming vias through the adhesive film, the patent creates a conductive path that allows the probing system to access and test replacement units without direct contact, thus maintaining wafer functionality while increasing the proportion of non-defective chips.
2Productivity
If replacement NAND chip units are mounted on defective units, then the percentage of non-defective chips increases, but the device structure and manufacturing process become more complex
Solution Approach 1:
The patent segments the wafer into multiple functional layers: the first wafer contains defective NAND chip units that serve as structural placeholders, while the second wafer contains replacement NAND chip units mounted on its back surface. This segmentation allows each layer to have a specific function, simplifying the overall design by clearly separating defective and replacement units into distinct structural zones.
Solution Approach 2:
The adhesive film performs multiple functions: it bonds the two wafers together mechanically, provides electrical insulation between layers, and allows via formation for electrical connection. This multi-functionality reduces the need for additional specialized components, thereby managing complexity while enabling the replacement mechanism.
3Loss of time
If all NAND chip units are probed, then comprehensive testing is achieved, but time is wasted probing defective units that cannot be used
Solution Approach 1:
The patent performs preliminary action by mounting replacement NAND chip units on the back surface of the wafer before the probing process. This allows the probing system to be redirected to test replacement units instead of wasting time on defective units, as the replacement units are already in position and electrically accessible through the adhesive film vias.
Solution Approach 2:
The probing process provides feedback about which NAND chip units are defective and which are functional. This feedback mechanism enables the system to identify and prioritize testing of replacement units, optimizing the probing sequence to focus on units that can contribute to the final product, thereby reducing time loss while maintaining accurate identification of non-defective units.
Data Source
AI summary
A storage wafer includes: a first semiconductor; a first element layer provided on the first semiconductor; a first pad provided on a first region of the first element layer; a second pad provided on a second region of the first element layer; an adhesive film provided on the second region; a second semiconductor provided on the adhesive film; a second element layer provided on the second semiconductor; and a third pad provided on the second element layer. The first element layer includes: first and second memory chip units coupled to the first and second pads, respectively. The second element layer includes an element coupled to the third pad and isolated from both the first and second pad.