Store Buffer Prefetching of Exclusive Cache State to Prevent Stalls
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Solution Overview
Problem
In modern computing devices with multiple CPUs, acquiring exclusive cache coherence state for store instructions involves significant latency due to system bus contention, leading to performance degradation and wasted power as CPUs stall while waiting for store instructions to complete.
Innovation Solution
Implement a gather buffer that performs pre-writes to acquire exclusive cache coherence state for store instructions, reducing latency by allocating cache lines and issuing pre-write requests to level 2 cache.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If store instructions are issued to the store buffer without prefetching exclusive cache coherence state, then the store buffer can operate with simple logic and fast issuance, but the exclusive cache coherence state may not be available when needed, causing store buffer stalls and reducing throughput
Solution Approach 1:
The patent applies preliminary action by prefetching exclusive cache coherence state entries from the L2 cache to the store buffer before the store instructions actually need them. The store buffer proactively monitors for potential exclusive state needs and initiates prefetch operations in advance, so that when a store instruction requires exclusive state, it is already available in the store buffer, eliminating stalls and maintaining high throughput.
2Productivity
If exclusive cache coherence state is prefetched proactively to the store buffer, then store buffer stalls are eliminated and throughput increases, but the store buffer complexity increases due to additional prefetching logic and state management
Solution Approach 1:
The patent applies segmentation by dividing the cache coherence state management into separate components: the L2 cache maintains the authoritative state, while the store buffer maintains a separate prefetch cache of exclusive states. This segmentation allows the store buffer to operate independently with its own simplified logic for monitoring and prefetching, rather than requiring complex integration with the L2 cache control logic, thus managing complexity while improving throughput.
Solution Approach 2:
The patent introduces an intermediary mechanism - a dedicated prefetch cache within the store buffer that acts as an intermediate storage layer between the L2 cache and the store instructions. This intermediary holds pre-fetched exclusive states, decoupling the complex L2 cache coherence management from the store buffer operations, and allowing the store buffer to simply retrieve from or refill the intermediary without direct L2 cache interaction for each store operation.
3Reliability
If the store buffer monitors and refills exclusive cache coherence state from the L2 cache, then the state is maintained for future store instructions, but the monitoring and refill operations increase the operational complexity and potential for stalls
Solution Approach 1:
The patent applies self-service by enabling the store buffer to autonomously monitor its own exclusive cache coherence state entries and automatically initiate refill operations from the L2 cache when needed. The store buffer includes logic that independently detects when exclusive states are missing or invalid and triggers prefetch/refill operations without requiring external control signals or complex coordination with the L2 cache, thereby maintaining reliability while preserving operational simplicity.
Data Source
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AI summary
A method, apparatus, and system for prefetching exclusive cache coherence state for store instructions is disclosed. An apparatus may comprise a cache and a gather buffer coupled to the cache. The gather buffer may be configured to store a plurality of cache lines, each cache line of the plurality of cache lines associated with a store instruction. The gather buffer may be further configured to determine whether a first cache line associated with a first store instruction should be allocated in the cache. If the first cache line associated with the first store instruction is to be allocated in the cache, the gather buffer is configured to issue a pre-write request to acquire exclusive cache coherency state to the first cache line associated with the first store instruction.