Store Buffer Error Recovery for Cache Misses
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Solution Overview
Problem
In data processing systems, cache miss errors during write allocation lead to substantial performance hits and data loss due to the inability to validate and store data in the linefill buffer, resulting in lost store data from non-writethrough store accesses.
Innovation Solution
Implementing a store buffer that stores non-writethrough store accesses in both the linefill buffer and the store buffer queue, with a bit indicating whether the access is conditional or unconditional, allowing for error recovery by converting conditional store accesses to unconditional ones upon cache line fetch errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If store data is placed in linefill buffer on cache miss, then cache update is enabled, but store data is lost when fetch error occurs
Solution Approach 1:
The patent creates a copy of store data in the store buffer queue alongside the linefill buffer storage. When a cache miss occurs, store data is duplicated: one copy goes to the linefill buffer for potential cache merging, and another copy is retained in the store buffer queue. This copying mechanism ensures that if the fetch operation fails and linefill buffer data is lost, the original store data remains preserved in the store buffer queue for later retrieval and memory writing.
2Reliability
If conditional store access is used in store buffer, then error recovery is enabled, but additional bookkeeping is required
Solution Approach 1:
The patent introduces a conditional store bit parameter in the store buffer queue entry to track the state of store data. When store data is duplicated to the store buffer queue, the conditional store bit is set to indicate that this is a conditional store awaiting fetch completion. Upon fetch error detection, the system changes the parameter state by clearing the conditional store bit and converting the conditional store to an unconditional store, enabling the buffered data to be written to memory without requiring complex recovery protocols.
3Stability of the object's composition
If store data is not written to memory immediately, then cache coherence is maintained, but performance hits occur on errors
Solution Approach 1:
The patent performs preliminary action by pre-copying store data to the store buffer queue before the fetch operation completes. This preliminary duplication ensures that if an error occurs during fetch, the store data is already safely stored in the store buffer queue and can be immediately written to memory without requiring complex error handling sequences. This preliminary preparation reduces performance impact by avoiding cascading error recovery operations.
Data Source
AI summary
A processor and cache is coupled to a system memory via a system interconnect. A first buffer circuit coupled to the cache receives one or more data words and stores the one or more data words in each of one or more entries. The one or more data words of a first entry are written to the cache in response to error free receipt. A second buffer circuit coupled to the cache has one or more entries for storing store requests. Each entry has an associated control bit that determines whether an entry formed from a first store request is a valid entry to be written to the system memory from the second buffer circuit. Based upon error free receipt of the one or more data words, the associated control bit is set to a value that invalidates the entry in the second buffer circuit based upon the error determination.