Store Buffer Forwarding Using Hash Code Address Matching
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Solution Overview
Problem
Pipelined processors face delays and increased power consumption due to the time-consuming process of comparing virtual and physical addresses in store buffer forwarding, especially in systems with virtual memory addressing, which can lead to processor wait states and performance issues.
Innovation Solution
A system and method that utilizes a hash code generated from address bits to quickly identify matching cache data in a store buffer, allowing for efficient data retrieval by selecting store buffer data if the hash code matches a stored hash code, thereby reducing the need for extensive address comparisons and minimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If virtual memory addressing is used with store buffer forwarding, then data retrieval from store buffer is enabled, but address comparison time increases and processor wait states are introduced
Solution Approach 1:
The patent extracts only the necessary address bits (index portion) for store buffer comparison, separating the address comparison function from full virtual-to-physical translation. This allows fast index matching without requiring complete address translation, thus reducing time loss while maintaining reliable data retrieval.
Solution Approach 2:
The store buffer stores pre-computed index values derived from virtual addresses during the store operation. When a load occurs, these pre-stored indices are immediately compared against the current address index without waiting for full address translation to complete, enabling early data availability.
2Reliability
If full address comparison is performed to ensure correct data retrieval, then data accuracy is maintained, but power consumption increases
Solution Approach 1:
The patent extracts only the index bits from the full address for comparison purposes, eliminating the need to process and compare complete virtual addresses. This selective comparison maintains data accuracy for store buffer hits while significantly reducing the energy consumption associated with full address translation and comparison.
Solution Approach 2:
The system performs partial address comparison (only index bits) rather than full address comparison. This partial action is sufficient to identify store buffer hits and avoid unnecessary full translation operations, reducing power consumption while maintaining the reliability needed for correct data retrieval.
3Reliability
If address translation is performed before store buffer comparison, then correct data location is identified, but data availability is delayed
Solution Approach 1:
The store buffer performs preliminary action by storing index values derived from virtual addresses during the store operation, before the corresponding load operation occurs. When the load occurs, these pre-computed indices enable immediate comparison and potential data retrieval without waiting for address translation to complete, thus improving data availability speed while maintaining location accuracy.
Solution Approach 2:
The patent extracts only the index portion of the address for storage and comparison in the store buffer, separating this fast index matching function from the slower full address translation process. This allows the system to maintain accurate data location identification through index matching while enabling faster data availability by avoiding the time-consuming full translation step.
Data Source
AI summary
The present disclosure describes a system and method for high performance, power efficient store buffer forwarding. Some illustrative embodiments may include a system, comprising: a processor coupled to an address bus; a cache memory that couples to the address bus and comprises cache data (the cache memory divided into a plurality of ways); and a store buffer that couples to the address bus, and comprises store buffer data, a store buffer way and a store buffer index. The processor selects the store buffer data for use by a data load operation if a selected way of the plurality of ways matches the store buffer way, and if at least part of the bus address matches the store buffer index.