Store Buffer Data Forwarding for Load Operation Efficiency
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Solution Overview
Problem
Current processor architectures face inefficiencies due to read/write competition in the instruction pipeline, particularly when store and load operations have memory dependencies, leading to stalls and reduced processing efficiency.
Innovation Solution
A method is introduced where a store buffer merges data at the same address and assembles data from both the store buffer and data cache to forward complete data to the load operation, eliminating the need for data to be written to the cache, thereby reducing waiting times and improving pipeline efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a store buffer is used to temporarily store store operation data, then read/write competition in the data cache can be avoided, but the load operation still must wait when there is memory dependency between load and store operations
Solution Approach 1:
The patent introduces a data forwarding mechanism that acts as an intermediary between the store buffer and load operation. When memory dependency is detected, the complete data from the store buffer is directly forwarded to the load operation without requiring the load to wait for cache write completion, thus eliminating the stall while maintaining data correctness.
Solution Approach 2:
The patent performs preliminary assembly of complete data in the store buffer before the load operation needs it. By detecting memory dependency early and assembling the complete data that the load operation will need, the system prepares the data in advance, allowing the load operation to proceed immediately without waiting for cache write completion.
2Productivity
If data is stored in the store buffer in words of multiple bytes, then the load operation can access data without waiting for cache write, but a complex assembling mechanism is required to assemble scattered data from multiple entries
Solution Approach 1:
The patent merges scattered data from multiple store buffer entries into a single complete data structure. When a load operation with memory dependency is detected, the system combines the relevant data portions from multiple store buffer entries into the complete data that the load operation requires, eliminating the need for complex per-load assembling mechanisms.
Solution Approach 2:
The store buffer is designed to automatically assemble complete data from its own internal entries when memory dependency is detected. The buffering unit itself performs the assembly function by detecting which entries contain data needed by the load operation and combining them, rather than requiring an external complex assembling mechanism.
3Speed
If the store buffer contains only a part of the data required by the load operation, then data can be forwarded quickly, but data parts need to be written into the data cache first which causes pipeline stall
Solution Approach 1:
The patent performs preliminary assembly of the complete data that the load operation requires, combining partial data from multiple store buffer entries before the load operation executes. This preliminary assembly eliminates the need to write partial data to cache and then stall for retrieval, as the complete data is already prepared in the store buffer.
Solution Approach 2:
The patent introduces a data forwarding mechanism that acts as an intermediary, taking partial data from the store buffer and assembling it into complete data that can be directly forwarded to the load operation. This intermediary assembly function eliminates the cache write-stall-read cycle by providing the complete data directly from the store buffer.
Data Source
AI summary
A processor and a method for executing load operation and store operation thereof are provided. The processor includes a data cache and a store buffer. When executing a store operation, if the address of the store operation is the same as the address of an existing entry in the store buffer, the data of the store operation is merged into the existing entry. When executing a load operation, if there is a memory dependency between an existing entry in the store buffer and the load operation, and the existing entry includes the complete data required by the load operation, the complete data is provided by the existing entry alone. If the existing entry does not include the complete data, the complete data is generated by assembling the existing entry and a corresponding entry in the data cache.