Store Buffer Merge Logic for Bus Traffic Reduction
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Solution Overview
Problem
In data processing systems, cache misses lead to increased bus traffic and reduced performance due to the need to write data directly to main memory, which is inefficient and burdensome.
Innovation Solution
Implementing a store buffer with a merge allowed indicator for each entry, which allows entries in the same memory line to be merged, reducing bus traffic and improving performance by consolidating writes into a single transaction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is written directly to main memory upon cache miss, then data is stored in memory, but bus traffic increases and performance decreases
Solution Approach 1:
The store buffer pre-stores write data in buffer entries before writing to main memory. When a cache miss occurs, the data is already prepared in the store buffer, eliminating the need for immediate memory access and reducing bus traffic while maintaining data storage reliability.
Solution Approach 2:
The store buffer acts as an intermediary between the cache and main memory. It temporarily holds write data and manages the timing of memory writes, allowing the processor to continue execution without waiting for slow memory operations, thus improving performance while ensuring data reaches memory reliably.
2Loss of energy
If multiple store buffer entries are merged into one, then bus traffic is reduced, but system complexity increases
Solution Approach 1:
Multiple store buffer entries that target the same memory location are merged into a single buffer entry. This consolidation reduces the number of separate write transactions to main memory, significantly reducing bus traffic and energy consumption while the merge management complexity is handled by the buffer's internal logic.
Solution Approach 2:
The store buffer automatically manages the merging of entries based on their memory addresses and coherency attributes. The system self-regulates by comparing entries and performing merges without external intervention, reducing bus traffic while keeping the complexity contained within the buffer module itself.
3Productivity
If store buffer merging is enabled for coherency regions, then performance is improved, but coherency management complexity increases
Solution Approach 1:
The store buffer applies different merge policies to different regions of memory based on their coherency attributes. Entries corresponding to coherency regions are marked with a specific attribute that enables merging, while other entries follow different rules. This localized approach improves performance for appropriate memory regions while maintaining proper coherency management through attribute-based differentiation.
Data Source
AI summary
In a data processing system, a store request is provided having corresponding store data and a corresponding access address, and a memory coherency required attribute corresponding to the access address of the store request is provided. When the store request results in a write-through store due to a cache hit or results in a cache miss, the corresponding access address and store data is stored in a selected entry of the store buffer and a merge allowed indicator is stored in the selected entry which indicates whether or not the selected entry is a candidate for merging. The merge allowed indicator is determined based on the memory coherency required attribute from the MMU and a store buffer coherency enable control bit of the cache. Entries of the store buffer which include an asserted merge allowed indicator and share a memory line in the memory are merged.