Store Buffer Segmentation for Direct Last-Level Cache Writes
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Solution Overview
Problem
In multi-core processing systems, the existing write-invalidate protocol for cache coherence is resource-intensive and time-consuming due to the need for snoop transactions across multiple cache levels, especially for frequently shared data, which hampers performance and efficiency.
Innovation Solution
Implementing a memory order buffer and store buffers with indicators to manage store transactions directly to a common last-level cache, allowing speculative stores to be resolved at the coherence point without querying lower caches, and using a separate buffer for coherent and non-coherent transactions to optimize cache coherence and reduce conflicts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the write-invalidate protocol is used for cache coherence, then cache coherence is maintained, but snoop transactions across multiple cache levels are resource-intensive and time-consuming
Solution Approach 1:
The patent segments store transactions into two categories: coherent store transactions (sent to lower caches) and non-coherent store transactions (sent directly to last-level cache). This segmentation allows the system to bypass snoop transactions for non-coherent stores while maintaining coherence for coherent stores, thereby reducing overall snoop transaction time while preserving cache coherence where needed.
Solution Approach 2:
The patent introduces a memory order buffer as an intermediary component that receives and manages store transactions. This buffer acts as a mediator between processor cores and the cache hierarchy, enabling direct storage to the last-level cache for non-coherent transactions without triggering snoop operations in lower caches, thus reducing the time overhead of the write-invalidate protocol.
2Reliability
If snoop transactions are performed across multiple cache levels, then cache coherence is ensured, but resource consumption increases
Solution Approach 1:
By segmenting store transactions into coherent and non-coherent categories, the patent enables the system to avoid unnecessary snoop transactions for non-coherent stores. This segmentation reduces the energy consumption associated with executing snoop transactions across multiple cache levels while maintaining cache coherence for transactions that require it.
3Device complexity
If a single store buffer is used for all transactions, then device complexity is reduced, but conflict resolution between coherent and non-coherent transactions becomes difficult
Solution Approach 1:
The patent divides the store buffer into separate buffers for coherent store transactions and non-coherent store transactions. This segmentation allows each buffer to be optimized for its specific transaction type, improving conflict resolution capability while maintaining manageable device complexity through specialized handling of each transaction category.
Solution Approach 2:
The patent applies local quality by creating specialized store buffers with different characteristics for different transaction types. The coherent store buffer is optimized for transactions requiring cache coherence, while the non-coherent store buffer is optimized for direct-to-last-level-cache transactions, allowing each buffer to have the specific properties needed for its intended purpose.
Data Source
AI summary
A system that uses a write-invalidate protocol has two types of stores: a traditional store that operates using a write-back policy that snoops for copies of the cache line at lower cache levels, and a store that writes, using a coherent write-through policy, directly to the last-level cache without snooping the lower cache levels. A separate store buffer may be maintained in the processor for the coherent write-through operations. A special bit may be maintained in the entries of a store buffer that is used for both traditional write-back policy stores and for coherent write-through policy. This bit indicates that loads and stores older than the last speculative store in the store buffer are allowed to be performed.