Store Buffer Segmentation for Load-Store Forwarding Latency
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Solution Overview
Problem
In modern microprocessors, the complexity of data forwarding from a store instruction to a load instruction during out-of-order execution is hindered by the addition of a priority encoder in the store to load forwarding path, which increases timing requirements and limits the maximum operating frequency, thereby affecting computing performance.
Innovation Solution
The method involves finding the correct store instruction corresponding to a load instruction in the first clock cycle and recording an indication, allowing store bypass data to be forwarded in a later clock cycle, while other out-of-order instructions execute, thereby hiding latency and reducing the clock cycle period by splitting the operations of finding and reading the required store instruction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a priority encoder is added in the store to load forwarding path to identify the youngest store entry, then the correctness of data forwarding is improved, but the timing requirement increases and the maximum operating frequency is limited
Solution Approach 1:
The patent segments the store buffer into multiple sets, with each set containing multiple entries. Instead of using a single priority encoder to select from all store entries, the system uses separate priority encoders for each set, which reduces the complexity and timing requirements of the forwarding path. This segmentation allows the system to maintain correctness while improving operating frequency.
Solution Approach 2:
The patent introduces a new dimension to the store buffer organization by using set indexing. The store buffer is organized as an array of sets, where each set can be independently indexed. This dimensional change allows the priority encoder to operate on a smaller subset of entries (within a set) rather than the entire store buffer, reducing the critical path timing.
2Productivity
If multiple issue and out-of-order execution are implemented to increase performance, then the instruction throughput is improved, but the data forwarding logic becomes more complex and requires more computational time
Solution Approach 1:
The patent segments the store buffer into multiple sets that can be independently managed. This segmentation simplifies the data forwarding logic by allowing the system to search within smaller set boundaries rather than searching the entire store buffer. The set-based organization reduces the computational complexity of identifying the youngest store entry while maintaining support for multiple issue and out-of-order execution.
Solution Approach 2:
The patent performs preliminary actions by pre-organizing store entries into sets with associated metadata (such as age information) that facilitates quick identification of the youngest entry. This preliminary organization reduces the computational burden during the forwarding decision process, enabling complex out-of-order execution without proportionally increasing forwarding logic complexity.
3Speed
If the store buffer search and data reading are performed in the same clock cycle, then the forwarding speed is improved, but the clock cycle period must be increased which limits processing frequency
Solution Approach 1:
The patent segments the store buffer search operation into set-based searches that can be completed within a shorter time frame. By organizing the store buffer into multiple small sets, the search operation within each set can be completed quickly, allowing the clock cycle period to be reduced while still achieving the necessary forwarding speed through parallel set processing.
Data Source
AI summary
A system and method for data forwarding from a store instruction to a load instruction during out-of-order execution, when the load instruction address matches against multiple older uncommitted store addresses or if the forwarding fails during the first pass due to any other reason. In a first pass, the youngest store instruction in program order of all store instructions older than a load instruction is found and an indication to the store buffer entry holding information of the youngest store instruction is recorded. In a second pass, the recorded indication is used to index the store buffer and the store bypass data is forwarded to the load instruction. Simultaneously, it is verified if no new store, younger than the previously identified store and older than the load has not been issued due to out-of-order execution.