Out-of-order Microprocessor Store Collision Avoidance

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Solution Overview

Problem

Out-of-order execution microprocessors face significant performance penalties due to store collisions, where load instructions receive incorrect data, requiring costly replays and increased pipeline traversal, which is inefficient and resource-intensive.

Innovation Solution

The implementation of a register alias table (RAT) that predicts store collisions by generating enhanced dependencies, causing load instructions to wait for the execution of dependent instructions, thereby avoiding replays and ensuring correct data retrieval without the need for re-execution.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the microprocessor executes instructions out of order to improve throughput, then productivity increases, but store collisions cause load instructions to receive incorrect data requiring costly replays

Engineering Contradiction:

Improveinstruction throughputVSAvoidreplay penalty

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by performing dependency checking and generating enhanced dependencies for load instructions before they are issued for execution. The register alias table proactively identifies potential store collision scenarios and prevents incorrect data retrieval by establishing proper instruction dependencies in advance, rather than detecting and correcting errors after they occur during execution.

Inventive Principle:

Principle #10Preliminary action

2Reliability

If the load instruction is replayed to receive correct store data, then data integrity is maintained, but the load instruction must wait many clock cycles and pass back through pipeline stages

Engineering Contradiction:

Improvedata integrityVSAvoidreplay waiting time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent prevents replay scenarios by performing preliminary dependency analysis when the load instruction is first encountered. The register alias table generates enhanced dependencies that ensure the load instruction will wait for the correct store instruction to complete before executing, thereby maintaining data integrity while avoiding the time penalty of replay operations.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback through the register alias table, which continuously monitors instruction dependencies and dynamically generates enhanced dependencies based on detected store collision patterns. This feedback mechanism allows the system to adaptively adjust instruction scheduling to prevent incorrect data retrieval, ensuring both reliability and efficiency.

Inventive Principle:

Principle #23Feedback

3Reliability

If a color bits array is used to track load-store dependencies, then store collision detection improves, but the array requires significant storage space and power consumption

Engineering Contradiction:

Improvestore collision detection accuracyVSAvoidcolor bits array size

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent extracts only the essential dependency information needed for store collision detection from the comprehensive color bits array approach. The register alias table selectively tracks and generates enhanced dependencies only for load instructions that are at risk of store collisions, rather than maintaining full color bit state for all instructions. This extraction reduces the storage requirements and power consumption while maintaining effective collision detection.

Inventive Principle:

Principle #2Taking out (Extraction)

Data Source

PatentUS8930679B2Out-of-order execution microprocessor with reduced store collision load replay by making an issuing of a load instruction dependent upon a dependee instruction of a store instruction

Publication Date: 2015.01.06 VIA TECH INC

AI summary

An out-of-order execution microprocessor for reducing the likelihood of having to replay a load instruction due to a store collision. The microprocessor includes a queue of entries, each entry configured to hold information that identifies sources of a store instruction used to compute its store address and to hold a dependency that identifies an instruction upon which the store instruction depends for its data. A register alias table (RAT), coupled to the queue of entries, is configured to encounter instructions in program order and to generate dependencies used to determine when the instructions may execute out of program order. In response to encountering a load instruction the RAT determines whether sources of the load instruction used to compute its load address match the sources of the store instruction in an entry of the queue, and if so, causes the load instruction to share the dependency of the matching store instruction.