Store Operation Commit Timing in Cache Arrays
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Solution Overview
Problem
Modern CPUs face challenges in reducing cache utilization busy times, particularly due to preemptive blocking that degrades cache availability and power consumption, as store operations are committed later in the pipeline, leading to longer busy times and inefficiencies in cache access.
Innovation Solution
The solution involves associating platform registers with a cache array, using a comparator to determine if multiple store operations target the same wordline, and delaying the commit of one store operation until the other's data is loaded, allowing simultaneous commitment to reduce busy times and power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If store operations are committed later in the pipeline, then cache availability is improved, but cache busy time increases and power consumption increases
Solution Approach 1:
The patent loads store operation control information and data into platform registers in advance, before the store operation is committed to the cache array. This preliminary loading allows the store operation to be ready for immediate commitment when the wordline becomes available, reducing the actual busy time while maintaining proper ordering.
Solution Approach 2:
The patent introduces platform registers as an intermediary component between the store operation pipeline and the cache array. These registers buffer the control information and data, allowing decoupling of the store operation initiation from the actual cache commitment, thereby reducing cache busy time while maintaining correctness.
2Reliability
If store operations are committed later in the pipeline, then cache availability is improved, but power consumption increases
Solution Approach 1:
The patent merges multiple store operations targeting the same wordline into a single simultaneous commit operation. By combining these operations, the wordline is activated only once, reducing the overall power consumption compared to separate activations for each store operation.
Solution Approach 2:
The patent performs preliminary comparison and grouping of store operations in platform registers before commitment. This allows the system to identify and merge operations targeting the same wordline, enabling a single activation event that reduces power consumption while maintaining cache availability.
3Productivity
If multiple store operations target the same wordline, then cache utilization improves, but commit timing complexity increases
Solution Approach 1:
The patent implements a self-service mechanism where the comparator automatically identifies when multiple store operations target the same wordline, and the buffer automatically delays commits to enable simultaneous execution. This self-organizing behavior reduces the need for complex external control logic.
Solution Approach 2:
The patent uses feedback from the comparator to control the buffer's delay behavior. When the comparator detects multiple operations targeting the same wordline, it provides feedback that triggers the buffer to delay commits, enabling automatic coordination without complex external timing control.
Data Source
AI summary
A computer product for reducing store operation busy times is provided and relates to associating first and second platform registers with a cache array, determining that first and second store operations target a same wordline of the cache array, loading control information and data of the store operations into the platform registers and delaying a commit of the first store operation until the loading of the second platform register is complete. The method further includes committing the data from the platform registers using the control information from the platform registers to the wordline of the cache array at a same time to thereby reduce a busy time of the wordline of the cache array.