Out-of-order processor store-hit-load detection
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Solution Overview
Problem
Out-of-order processors face significant performance penalties due to store-hit-loads (SHLs) when younger load instructions execute ahead of older store instructions, leading to pipeline flushes and re-fetching of instructions, which can be costly in terms of processor performance.
Innovation Solution
A technique that involves maintaining a store-hit-load (SHL) table to track store addresses and update counts for SHL entries, creating dependencies for load instructions that overlap with store instructions, thereby stalling younger load instructions until the older store instruction executes, thereby minimizing pipeline flushes and maintaining program consistency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If out-of-order execution is permitted for load and store instructions, then processor performance is improved through parallel execution, but store-hit-loads cause pipeline flushes and severe performance penalties
Solution Approach 1:
The patent applies preliminary action by detecting store-hit-load conditions before the load instruction executes. The system monitors the load reorder queue and detects when a store instruction's real address matches a load instruction's real address in the queue, allowing early intervention to prevent pipeline flushes while maintaining program consistency
Solution Approach 2:
The patent implements feedback mechanisms where the system continuously monitors execution status and detects SHL conditions. When a store instruction is issued, the system checks against the load reorder queue, and upon detecting a match, triggers appropriate control signals to prevent the load from executing out of order, thereby maintaining consistency while allowing out-of-order execution to continue elsewhere
2Device complexity
If store-hit-loads are detected late in the instruction execution pipeline, then detection complexity is reduced, but recovery penalties increase due to invalidating instructions and reissuing
Solution Approach 1:
The system performs preliminary detection of store-hit-load conditions by checking the load reorder queue when a store instruction is issued, well before the load instruction would execute. This early detection allows the system to prevent the harmful condition before it occurs, avoiding the need for costly pipeline recovery operations
Solution Approach 2:
The patent introduces an intermediary detection mechanism between the store instruction issuance and the load instruction execution. The load reorder queue serves as an intermediary structure that allows the system to check for potential SHL conditions without requiring complex analysis of all possible instruction combinations, thus reducing detection complexity while enabling early intervention
3Productivity
If a store barrier cache is used to predict store-hit-loads, then pipeline flushes are reduced, but device complexity increases due to additional cache structures
Solution Approach 1:
The patent makes the load reorder queue serve multiple functions: it maintains its primary function of tracking load instructions for out-of-order execution while also serving as a detection structure for store-hit-load conditions. This eliminates the need for a separate store barrier cache, reducing device complexity while maintaining the ability to predict and prevent SHL conditions
Solution Approach 2:
The system merges the detection function into the existing load reorder queue structure rather than implementing a separate store barrier cache. By combining these functions, the patent reduces the overall device complexity while maintaining the effectiveness of SHL prediction and prevention, allowing out-of-order execution to proceed without unnecessary pipeline flushes
Data Source
AI summary
A technique for reducing store-hit-loads in an out-of-order processor includes storing a store address of a store instruction associated with a store-hit-load (SHL) pipeline flush in an SHL entry. In response to detecting another SHL pipeline flush for the store address, a current count associated with the SHL entry is updated. In response to the current count associated with the SHL entry reaching a first terminal count, a dependency for the store instruction is created such that execution of a younger load instruction with a load address that overlaps the store address stalls until the store instruction executes.