Store-to-Load Forwarding Correctness Checks at Store Commit
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Solution Overview
Problem
Cache memories in microprocessors impact performance due to access time and capacity issues, which affect instruction execution rates and cache coherency in multi-processor systems.
Innovation Solution
Implementing a load queue, store queue, and load/store unit to record and check forwarding behavior for store and load instructions, using physical address proxies (PAPs) to enhance cache coherence and reduce unnecessary processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If store-to-load forwarding is implemented to improve instruction execution rate, then processor performance improves, but correctness errors may occur due to premature forwarding before store commit
Solution Approach 1:
The patent records forwarding behavior in advance during load instruction execution, but delays the validation check until after the store instruction commits. This preliminary recording followed by deferred verification allows the system to prepare forwarding information early while ensuring correctness is validated only when the store data is guaranteed to be available, thus maintaining both high execution rate and forwarding correctness.
2Productivity
If cache capacity is increased to improve hit rate, then processor performance improves, but physical size and area increase
Solution Approach 1:
The patent extracts the forwarding validation logic from the main cache access path and places it in a separate verification mechanism that operates during store commit. This allows the cache itself to remain compact while adding correctness checking functionality elsewhere in the system, separating the capacity function from the validation function.
3Speed
If cache access time is reduced to improve processor cycle time, then instruction execution speed improves, but cache capacity and hit rate may be affected
Solution Approach 1:
The patent segments the cache access operation into distinct phases: a fast access phase for retrieving data quickly, and a separate validation phase for verifying forwarding correctness. This segmentation allows the critical data access path to remain fast while the correctness verification occurs in parallel or subsequently, preventing speed optimizations from compromising hit rate.
Data Source
AI summary
A microprocessor includes a load queue, a store queue, and a load/store unit that, during execution of a store instruction, records store information to a store queue entry. The store information comprises store address and store size information about store data to be stored by the store instruction. The load/store unit, during execution of a load instruction that is younger in program order than the store instruction, performs forwarding behavior with respect to forwarding or not forwarding the store data from the store instruction to the load instruction and records load information to a load queue entry, which comprises load address and load size information about load data to be loaded by the load instruction, and records the forwarding behavior in the load queue entry. The load/store unit, during commit of the store instruction, uses the recorded store information and the recorded load information and the recorded forwarding behavior to check correctness of the forwarding behavior.