Store-to-load forwarding via operand source comparison
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Solution Overview
Problem
Current microprocessors face inefficiencies in store-to-load forwarding due to time-consuming virtual address comparisons, which lead to increased false collision detections, power consumption, and die real estate issues, necessitating a more accurate and efficient method for detecting store collisions.
Innovation Solution
The implementation of a microprocessor with a queue holding store information and control logic that predicts store forwarding by comparing the sources of operands used to calculate load and store addresses, rather than the addresses themselves, and maintaining a replay history to enhance prediction accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If virtual address comparison is used for store collision detection, then store forwarding can be implemented, but the process is time-consuming and affects maximum clock frequency
Solution Approach 1:
The patent segments the virtual address comparison into two parts: comparing only the index portion of the virtual address (which is sufficient for collision detection) and performing the full physical address comparison only when needed. This segmentation reduces the critical path time while maintaining forwarding accuracy.
Solution Approach 2:
The patent performs preliminary action by comparing the index portions of virtual addresses in advance to identify potential collisions before the full physical address comparison is needed. This preliminary comparison allows the system to prepare for forwarding decisions without waiting for the complete address translation and comparison process.
2Measurement precision
If full virtual address comparison is performed, then store collision detection accuracy is improved, but power consumption and die real estate increase
Solution Approach 1:
The patent segments the address comparison by focusing only on the index portion of virtual addresses for the initial collision detection phase. This segmentation uses fewer comparators and less power while maintaining sufficient accuracy. Full physical address comparison is reserved only for verification when needed.
Solution Approach 2:
The patent applies partial action by comparing only the necessary portion (index) of the virtual address for store collision detection, rather than comparing the full virtual address. This partial comparison provides sufficient accuracy for forwarding decisions while significantly reducing power consumption and comparator requirements.
3Productivity
If virtual address comparison is used for store forwarding, then forwarding can proceed in parallel with translation, but false collision detections increase
Solution Approach 1:
The patent segments the address comparison into index portion comparison (for efficient parallel forwarding) and physical address comparison (for accurate verification). This segmentation allows the system to benefit from both fast parallel processing and accurate collision detection by using the appropriate comparison level at the appropriate stage.
Solution Approach 2:
The patent implements feedback by using the physical address comparison result to verify or correct the virtual address-based forwarding decision. If the physical address comparison shows a mismatch, the system can replay the load instruction to ensure correct data retrieval. This feedback mechanism maintains reliability while preserving forwarding efficiency.
Data Source
AI summary
A microprocessor includes a queue comprising a plurality of entries each configured to hold store information for a store instruction. The store information specifies sources of operands used to calculate a store address. The store instruction specifies store data to be stored to a memory location identified by the store address. The microprocessor also includes control logic, coupled to the queue, configured to encounter a load instruction. The load instruction includes load information that specifies sources of operands used to calculate a load address. The control logic detects that the load information matches the store information held in a valid one of the plurality of queue entries and responsively predicts that the microprocessor should forward to the load instruction the store data specified by the store instruction whose store information matches the load information.