Store Queue Load Forwarding Re-execution Eligibility
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Solution Overview
Problem
Cache memories in microprocessors face challenges in improving processor performance due to access time and cache coherency issues, particularly in multi-processor systems where ensuring the latest data values across caches is crucial.
Innovation Solution
The implementation of a microprocessor with a cache memory, a store queue, and a load/store unit that determines if store data in the store queue overlaps with load data, canceling the load instruction execution if there's overlap and indicating that the load instruction is not eligible to re-execute until the older store instruction updates the cache memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the processor checks for store-to-load forwarding opportunities, then instruction execution rate improves, but processor complexity increases due to additional queue structures and comparison logic
Solution Approach 1:
The processor divides the store-to-load forwarding mechanism into separate components: a store queue for tracking store instructions, a load queue for tracking load instructions, and comparison logic that operates independently for each load instruction. This segmentation allows the system to manage complexity by handling forwarding checks in a modular fashion rather than as a monolithic structure.
Solution Approach 2:
The patent introduces intermediate data structures including store queue entries and load queue entries that act as mediators between store instructions and load instructions. These entries contain address information and data values that facilitate the forwarding decision process without requiring direct complex interactions between all processor components.
2Measurement precision
If the processor implements store-to-load forwarding with full address comparison, then data forwarding accuracy improves, but processing time increases due to additional comparison operations
Solution Approach 1:
The processor performs preliminary actions by pre-computing and storing address information in the store queue entries when store instructions are executed. This includes calculating address tags and storing them in advance, so that when a load instruction needs forwarding, the comparison can use pre-prepared data rather than computing everything from scratch at the moment of forwarding decision.
3Reliability
If the processor allows load instruction re-execution after store queue updates, then cache coherency improves, but instruction execution time increases due to re-execution delays
Solution Approach 1:
The patent implements a feedback mechanism where the load queue entry receives updates from the store queue when store instructions complete execution. The load instruction can be re-executed based on feedback information indicating that the store has completed and the data is now available in the cache, allowing the processor to dynamically adjust execution timing based on actual cache state rather than using fixed conservative timing.
Data Source
AI summary
A microprocessor includes a cache memory, a store queue, and a load/store unit. Each entry of the store queue holds store data associated with a store instruction. The load/store unit, during execution of a load instruction, makes a determination that an entry of the store queue holds store data that includes some but not all bytes of load data requested by the load instruction, cancels execution of the load instruction in response to the determination, and writes to an entry of a structure from which the load instruction is subsequently issuable for re-execution an identifier of a store instruction that is older in program order than the load instruction and an indication that the load instruction is not eligible to re-execute until the identified older store instruction updates the cache memory with store data.