Store Queue Offset Comparison for RAW Hazard Detection
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Solution Overview
Problem
In out-of-order processors, the delay in determining store-load dependencies due to the unavailability of memory addresses reduces instruction-level parallelism and processor throughput, as loads must wait for the store address to be generated, even if the offset is known and distinct from store addresses.
Innovation Solution
The system compares object identifiers (OIDs) and offsets for load instructions against those in the store queue, allowing early determination of read-after-write hazards and enabling cache access without waiting for the store address, by using augmented store queue entries with valid flags for OIDs and offsets, and performing cache access if no hazard exists.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the system waits for the store address to be generated before determining store-load dependencies, then address comparison accuracy is improved, but instruction-level parallelism and processor throughput deteriorate
Solution Approach 1:
The patent applies preliminary action by performing partial address comparison using the offset field before the complete store address is available. The offset, being a constant or immediately available value, is used in advance to eliminate non-dependent stores from the comparison set, allowing load instructions to proceed without waiting for the full store address to be generated.
Solution Approach 2:
The patent segments the memory address into two components: the offset (which is immediately available) and the base address (which requires waiting). By separating these components and performing comparison operations on the offset segment first, the system achieves early dependency elimination without compromising the accuracy of the final address comparison.
2Measurement precision
If the system compares complete addresses to determine store-load dependencies, then dependency detection accuracy is improved, but instruction execution speed deteriorates
Solution Approach 1:
The system performs preliminary dependency detection using the offset field before the complete address is available. This preliminary action filters out obviously non-dependent store-load pairs early in the process, allowing the majority of load instructions to execute without waiting for complete address generation, while maintaining accurate dependency detection for cases where offsets match.
Solution Approach 2:
The patent applies partial action by performing an incomplete comparison using only the offset field initially. This partial comparison is sufficient to eliminate many non-dependent cases, and the system accepts that some false positives may occur but will be resolved when complete addresses become available, thereby achieving acceptable dependency detection accuracy with improved execution speed.
3Reliability
If the system waits for all store addresses to be available before processing load instructions, then memory consistency is improved, but processor throughput deteriorates
Solution Approach 1:
The system performs preliminary filtering of store instructions using the offset field before the complete store address is available. This preliminary action identifies and eliminates stores that cannot possibly conflict with the load instruction, allowing the load to proceed to cache access while maintaining memory consistency for cases where offsets match and complete address comparison will confirm dependency.
Solution Approach 2:
The patent implements a dynamic dependency checking mechanism where the depth and completeness of address comparison adapts based on available information. When offsets differ, the system performs only partial comparison and allows immediate cache access. When offsets match, the system dynamically waits for complete addresses to perform full verification, thereby maintaining memory consistency only when necessary while maximizing throughput in the common case of non-dependent operations.
Data Source
AI summary
One embodiment of the present invention provides a system that processes memory-access instructions in an object-addressed memory hierarchy. During operation, the system receives a load instruction to be executed, wherein the load instruction loads a data item from an object, and wherein the load instruction specifies an object identifier (OID) for the object and an offset for the data item within the object. Next, the system compares the OID and the offset for the data item against OIDs and offsets for outstanding store instructions in a store queue. If the offset for the data item does not match any of the offsets for the outstanding store instructions in the store queue, and hence no read-after-write (RAW) hazard exists, the system performs a cache access to retrieve the data item for the load instruction.