Store Queue Physical Address Proxies for Cache Coherency
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Cache memories in microprocessors face challenges in reducing access time and improving cache coherency, particularly in multi-processor systems, where cache coherency protocols like write-invalidate can be inefficient due to the need to manage extensive cache coherence-related information, leading to increased latency and processor performance bottlenecks.
Innovation Solution
Implementing a physically-indexed physically-tagged second-level set-associative cache with a store queue that uses store physical address proxies (PAPs) to efficiently manage cache coherence, allowing the load unit to forward store data based on PAPs during load instructions, thereby reducing the need for physical address comparisons and improving cache access times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If cache memories store extensive cache coherence-related information to maintain coherency in multi-processor systems, then cache coherency is maintained, but cache access time increases and processor performance decreases
Solution Approach 1:
The patent extracts the cache coherence management function from the main cache structure by introducing a separate store queue. This queue holds store instructions and their physical address proxies independently, allowing the cache to focus on fast data access while the queue handles coherence protocols, thereby reducing cache access time while maintaining coherency.
Solution Approach 2:
The store queue acts as an intermediary between store instructions and the cache memory. It buffers store operations and uses physical address proxies to track cached data without requiring full cache line comparisons, enabling efficient coherence management that doesn't bottleneck cache access performance.
2Reliability
If cache memories hold more information including tags, status, and replacement policy, then cache coherency and management are improved, but the physical size of the cache increases
Solution Approach 1:
The patent uses physical address proxies as simplified copies of full physical addresses in the store queue. These proxies contain only the essential information needed to identify cached data (set index and way number), eliminating the need to store extensive coherence information in the main cache structure, thus reducing physical size while maintaining management capability.
3Area of stationary object
If the cache memory capacity is reduced to decrease physical size, then the physical footprint is smaller, but the cache hit rate decreases
Solution Approach 1:
The store queue serves multiple functions: it buffers store instructions, tracks cached data using physical address proxies, enables store-to-load forwarding, and manages cache coherence. This multi-functionality allows the system to maintain effective cache management with smaller capacity by efficiently utilizing the available space for high-impact operations.
4Measurement precision
If physical address comparisons are performed for store-to-load forwarding, then forwarding accuracy is improved, but the time required for address matching increases
Solution Approach 1:
The patent changes the parameter used for address matching from full physical addresses to compressed physical address proxies. These proxies retain the critical set index and way number bits needed for accurate matching while reducing the total number of bits compared, enabling fast comparison that doesn't sacrifice forwarding accuracy.
Data Source
AI summary
A microprocessor includes a store queue (SQ) and a physically-indexed physically-tagged second-level set-associative cache. Each cache entry is uniquely identified by a set index and a way number. Each SQ entry holds information for a store instruction. The information includes store data to be written to a store physical address, a portion of which is a store physical line address. The information also includes a store physical address proxy (PAP) for the store physical line address. The store PAP specifies the set index and the way number of the cache entry into which a cache line specified by the store physical line address is allocated. A load unit, during execution of a load instruction, uses the store PAP held in a SQ entry in making a decision whether to forward to the load instruction the store data held in the SQ entry.