Store Queue Priority Handling for Expedited Store Operations
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Solution Overview
Problem
Conventional multiprocessor systems experience performance delays due to store gathering in the store queue, which can negatively impact the servicing of store operations and other instructions or threads.
Innovation Solution
The proposed solution involves marking certain store operations as high priority, allowing them to be expedited through the store queue by reducing or eliminating store gathering and prioritizing their dispatch, thereby reducing delays and improving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If store gathering is implemented in the store queue to reduce the number of store accesses to cache, then the overall number of store operations is reduced, but the delay in servicing store operations increases and performance of other instructions and threads is negatively impacted
Solution Approach 1:
The patent segments store operations into two priority categories: high-priority store operations (marked by barrier instructions) and standard-priority store operations. The store queue is divided into separate handling paths, with high-priority operations bypassing the store gathering process and being serviced immediately, while standard operations undergo store gathering to reduce cache accesses. This segmentation resolves the contradiction by allowing time-sensitive operations to be serviced without delay while still achieving reduced cache accesses for non-critical operations.
Solution Approach 2:
The patent implements dynamic priority assignment to store operations based on the presence of barrier instructions in the instruction sequence. Store operations are dynamically marked as high-priority when preceded by barrier instructions, causing the store queue to adapt its handling behavior in real-time. This dynamic approach allows the system to optimize between reducing cache accesses and minimizing service delay based on the specific characteristics of each store operation.
2Productivity
If store gathering combines multiple store operations into a single store queue entry, then efficiency of store operations is increased, but the servicing of store operations is delayed
Solution Approach 1:
The patent segments the store queue processing into two distinct efficiency paths: high-priority store operations bypass the store gathering mechanism entirely and are serviced individually with high speed, while standard-priority operations utilize store gathering to combine multiple operations into single cache accesses, achieving higher overall efficiency. This segmentation allows the system to optimize for speed when needed and for efficiency when possible.
Solution Approach 2:
The patent changes the operational parameters of store queue entries based on priority marking. High-priority store operations are assigned parameters that disable store gathering and enable immediate servicing, while standard operations use parameters that enable store gathering and deferred servicing. This parameter change approach allows the same store queue hardware to operate in two different modes, resolving the contradiction between efficiency and speed.
Data Source
AI summary
In at least some embodiments, a processor core generates a store operation by executing a store instruction in an instruction sequence. The store operation is marked as a high priority store operation in response to detecting a barrier instruction in the instruction sequence immediately preceding the store instruction in program order and is not so marked otherwise. The store operation is buffered in a store queue associated with a cache memory of the processor core. Handling of the store operation in the store queue is expedited in response to the store operation being marked as a high priority store operation and not expedited otherwise.