Store Queue Architecture for Speculative Execution

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Solution Overview

Problem

Conventional store queue designs for processors are limited by their inability to efficiently handle speculative execution, cache misses, and out-of-order re-execution of deferred loads or stores, particularly due to buffering limitations and insufficient bandwidth, which leads to performance issues and idle processor time.

Innovation Solution

A store queue architecture that buffers stores during speculative execution, using a content-addressable memory (CAM) to manage entries with byte masks and age counters, allowing for merging of stores, deferring of loads with unknown addresses, and efficient re-execution in deferred mode, while maintaining exclusive access to cache lines through store-marking.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional store queue designs buffer each store to an individual store queue entry, then store operations can be buffered, but the memory system must provide sufficient bandwidth to retire each store and the processor idle time increases during cache misses

Engineering Contradiction:
Improvestore operation correctnessVSAvoidprocessor idle time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent merges multiple stores into a single store queue entry when they target the same memory location. Instead of maintaining separate entries for each store, the system combines them and tracks which bytes have been stored using a byte mask. This reduces the number of entries that must be retired and decreases processor idle time during cache misses.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent implements dynamic store queue entry management where entries can be merged or split based on the store operation. The byte mask dynamically tracks which bytes have been stored, allowing the system to adaptively manage store queue contents and optimize retirement bandwidth requirements.

Inventive Principle:
Principle #15Dynamics

2Measurement precision

If conventional store queue designs provide circuitry to produce the most recent value of every byte in the store queue, then load operations can be correctly matched against stores, but the device complexity increases

Engineering Contradiction:
Improveload-store matching accuracyVSAvoidstore queue circuitry complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent segments the store queue into multiple independent banks, where each bank handles a subset of store operations. This segmentation allows parallel processing of store and load operations across different banks, reducing the complexity of byte production circuitry while maintaining accurate load-store matching through localized byte masks in each bank.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a byte mask as an intermediary data structure that tracks which bytes have been stored without requiring complex circuitry to produce every possible byte value. The byte mask serves as a mediator between the simplified store buffering mechanism and the load operation that needs to know which bytes are available.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If conventional program-order store queue designs are used, then stores can be buffered in program order, but speculative execution with unknown values and out-of-order re-execution of deferred loads or stores are not supported

Engineering Contradiction:
Improvespeculative execution capabilityVSAvoidexecution mode flexibility
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

The patent designs the store queue to serve multiple execution modes (in-order and speculative) simultaneously. The same store queue infrastructure supports both conventional program-order execution and speculative execution with unknown values, providing universal functionality across different execution paradigms without requiring separate dedicated structures.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent changes the operational parameters of the store queue based on execution mode. During speculative execution, the store queue accepts and buffers stores with unknown values, setting corresponding flags in the byte mask. When switching to in-order execution, the same structure operates with full value validation. This parameter-based adaptation enables versatility without structural complexity.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS7849290B2Store queue architecture for a processor that supports speculative execution
Publication Date: 2010.12.07 ORACLE AMERICAN INC
  • US7849290B2 patent drawing
  • US7849290B2 patent drawing
  • US7849290B2 patent drawing

AI summary

Embodiments of the present invention provide a system that buffers stores on a processor that supports speculative execution. The system starts by buffering a store into an entry in the store queue during a speculative execution mode. If an entry for the store does not already exist in the store queue, the system writes the store into an available entry in the store queue and updates a byte mask for the entry. Otherwise, if an entry for the store already exists in the store queue, the system merges the store into the existing entry in the store queue and updates the byte mask for the entry to include information about the newly merged store. The system then forwards the data from the store queue to subsequent dependent loads.