Store Queue Zombie Entries Extend Load Forwarding
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Solution Overview
Problem
In processor cores with a no-write allocate cache policy, store misses can cause significant delays as loads must wait for stores to drain to the next level of cache, leading to inefficiencies, especially when store forwarding mechanisms are costly and not suited for all workload types.
Innovation Solution
The method extends store forwarding by maintaining zombie store entries in the store queue with a zombie stat bit, allowing these entries to be utilized by the processor core even after being drained to the L2 cache, and deallocating them as needed to accommodate newer stores, thus extending the window for load forwarding without adding expensive queues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If store forwarding is implemented for cache misses, then load forwarding capability is improved, but device complexity and cost increase due to requiring additional queues
Solution Approach 1:
The store queue is enhanced with a zombie stat bit to serve dual purposes: it continues to handle normal store operations while also maintaining zombie store entries for extended store forwarding. This multi-functional approach enables load forwarding for cache misses without requiring separate dedicated queues, thus improving productivity while avoiding additional device complexity
Solution Approach 2:
The invention introduces a new parameter (zombie stat bit) to the existing store queue entries, transforming their state to indicate whether they are zombie stores. This parameter change allows the same hardware structure to support extended store forwarding functionality without physical expansion, resolving the contradiction between improved forwarding capability and device complexity
2Quantity of substance
If stores are drained to L2 cache immediately, then cache memory usage is optimized, but load forwarding window is reduced causing delays
Solution Approach 1:
The system performs preliminary draining of stores to L2 cache while simultaneously maintaining zombie store entries in the store queue. This preliminary action allows L2 cache to be populated early, optimizing memory usage, while the zombie entries preserve the forwarding window for loads that may still need the data, thus reducing forwarding delays without sacrificing memory efficiency
Solution Approach 2:
The zombie store entries act as an intermediary between the L2 cache and load instructions. Even after stores are drained to L2, the zombie entries in the store queue serve as a mediator that maintains the forwarding path, allowing loads to access data through the store queue without waiting for L2 cache operations, thereby reducing delays while maintaining efficient cache memory usage
3Duration of action of moving object
If zombie store entries are maintained in STQ, then store forwarding window is extended, but STQ resource availability for new stores is reduced
Solution Approach 1:
The system implements a dynamic management strategy where zombie store entries are maintained only when beneficial for forwarding and are automatically discarded when the store queue needs capacity for new stores. The zombie stat bit enables selective retention and disposal of zombie entries, extending the forwarding window when resources are available while recovering queue capacity when needed, thus balancing forwarding duration with queue resource availability
Data Source
AI summary
A load store unit (LSU) in a processor core detects that new data produced by the processor core is ready to be drained to an L2 cache. In response to the LSU detecting that an earlier version of the new data is not stored in L1 cache, a memory controller sends the new data as L1 cache missed data to a store queue (STQ), where the STQ makes data available for deallocation from the STQ to the L2 cache. In response to determining that there is no newer data waiting to be stored in the STQ, or no cache line invalidate to the line containing the store data in the STQ that misses the cache, the memory controller maintains the new data in the STQ with a zombie stat bit that indicates that the new data is a zombie store entry that can be utilized by the processor core.