Store Reorder Queue Drain Delay for TLBI Coherence
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Solution Overview
Problem
In a multiprocessor system, the propagation time of a TLBI instruction can lead to issues with cache coherence due to the potential for incomplete SRQ drainage before acknowledgement, causing outdated values to be read by processing elements, which affects the visibility of store instruction results.
Innovation Solution
Applying a delay to the drain cycle of the SRQ allows additional time to validate SRQ logic functionality, increasing the chances of identifying potential problems and ensuring complete drainage before sending acknowledgements, thus maintaining cache coherence.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the SRQ drain cycle is completed quickly, then processing efficiency is improved, but cache coherence may be compromised due to incomplete drainage before TLBI propagation
Solution Approach 1:
The patent applies preliminary action by delaying the SRQ drain cycle to ensure complete drainage before TLBI propagation. The drain cycle is postponed until after the invalidation instruction has been propagated across the interconnect, guaranteeing that all processing elements receive the invalidation signal before store data is drained to cache or memory. This prevents coherence violations while maintaining systematic control over the timing sequence.
Solution Approach 2:
The patent implements dynamics by making the SRQ drain cycle timing adaptive rather than fixed. The drain cycle duration is dynamically adjusted based on the propagation time of the TLBI instruction across the interconnect. This dynamic timing ensures that the drain operation completes at the optimal moment - after invalidation propagation is complete - thereby maintaining cache coherence while minimizing unnecessary delays to processing efficiency.
2Speed
If the TLBI instruction propagation time is reduced, then system responsiveness is improved, but SRQ drainage may be incomplete leading to outdated values being read
Solution Approach 1:
The patent applies preliminary action by ensuring the SRQ drainage operation is completed as a preliminary step before any processing element can read data that might be affected by the TLBI invalidation. The drain cycle is scheduled to complete before the propagation of the invalidation signal finishes, guaranteeing that all store data is properly transferred to cache or memory before invalidation takes effect, thus preventing outdated value reads.
Solution Approach 2:
The patent implements feedback by monitoring the completion status of the SRQ drain cycle and using this information to control the timing of TLBI propagation. The system waits for confirmation that drainage is complete before allowing the invalidation instruction to propagate, creating a feedback loop that ensures data visibility reliability while maintaining efficient instruction propagation speed.
Data Source
AI summary
Systems and methods for invalidating page translation entries are described. A processing element may apply a delay to a drain cycle of a store reorder queue (SRQ) of a processing element. The processing element may drain the SRQ under the delayed drain cycle. The processing element may receive a translation lookaside buffer invalidation (TLBI) instruction from an interconnect connecting the plurality of processing elements. The TLBI instruction may be an instruction to invalidate a translation lookaside buffer (TLB) entry corresponding to at least one of a virtual memory page and a physical memory frame. The TLBI instruction may be broadcasted by another processing element. The application of the delay to the drain cycle of the SRQ may decrease a difference between the drain cycle of the SRQ and an invalidation cycle associated with the TLBI.