Store-to-load forwarding physical address proxy matching

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Solution Overview

Problem

High-performance microprocessors face challenges in preventing side channel attacks (SCAs) without lengthening the execution pipeline or sacrificing performance, as conventional processors rely on speculative execution which creates vulnerabilities through incomplete physical address comparisons and time-consuming tablewalks.

Innovation Solution

Implementing a high-performance, speculative out-of-order executing super-scalar processor with a short execution pipeline that conditions store-to-load forwarding on complete physical address matching, using physical address proxies (PaPs) to speed up comparisons and reduce the number of bits compared, and incorporating a memory dependence predictor to minimize delays.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If speculative execution is used to enhance performance, then processing speed is improved, but vulnerability to side channel attacks increases

Engineering Contradiction:
Improveprocessing speedVSAvoidsecurity against side channel attacks
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent performs preliminary physical address comparison and permission validation before speculative store-to-load forwarding occurs. By checking whether the physical addresses match and permissions are valid in advance, the system can safely speculate on data forwarding without creating security vulnerabilities. This preliminary validation prevents mis-speculation that could lead to side channel attacks while maintaining performance benefits.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If complete physical address comparison is performed before forwarding, then security is improved, but execution pipeline length increases

Engineering Contradiction:
Improvesecurity against side channel attacksVSAvoidexecution pipeline length
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts the critical security-checking functions (physical address comparison and permission validation) from the main execution pipeline and performs them in parallel or out-of-order. This allows the essential security validations to occur without forcing sequential execution and pipeline lengthening, maintaining both security and performance.

Inventive Principle:
Principle #2Taking out (Extraction)

3Measurement precision

If physical address comparison is performed before forwarding, then accuracy of forwarding is improved, but time consumption increases

Engineering Contradiction:
Improveaddress matching accuracyVSAvoidforwarding delay
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent changes the parameter being compared from virtual addresses to physical addresses for the store-to-load forwarding decision. By using physical addresses (which are translated early in the pipeline) and permission bits, the system achieves accurate address matching without the time penalty of waiting for complete tablewalk operations, as the physical address is available earlier than the final virtual address translation.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11989285B2Thwarting store-to-load forwarding side channel attacks by pre-forwarding matching of physical address proxies and/or permission checking
Publication Date: 2024.05.21 VENTANA MICRO SYSTEMS INC
  • US11989285B2 patent drawing
  • US11989285B2 patent drawing
  • US11989285B2 patent drawing

AI summary

A method and system for mitigating against side channel attacks (SCA) that exploit speculative store-to-load forwarding is described. The method comprises ensuring that the physical load and store addresses match and/or that permissions are present before speculatively store-to-load forwarding. Various improvements maintain a short load-store pipeline, including usage of a virtual level-one data cache (DL1), usage of an inclusive physical level-two data cache (DL2), storage and lookup of physical data address equivalents in the DL1, and using a memory dependence predictor (MDP) to speed up or replace store queue camming of load data addresses against store data addresses.