Store Unit ALU Integration for Microprocessor Forwarding Delay
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Solution Overview
Problem
In microprocessors with load/store architecture, valuable time is consumed in transferring results between distinct load/store units and arithmetic/logical units due to signal forwarding delays, which can amount to one or more clock cycles depending on the layout and process technology.
Innovation Solution
Integrating an arithmetic/logic unit (ALU) into the load unit and store unit, allowing these units to perform arithmetic/logical operations directly on data fetched from memory before loading or storing, thereby eliminating the need for result forwarding to separate execution units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If distinct load/store units and arithmetic/logical units are separated, then the units may be simpler and faster, but valuable time is consumed in the transfer of results between units through forwarding buses
Solution Approach 1:
The patent merges the arithmetic/logical unit with the store unit to form an integrated execution unit. This combination eliminates the need to forward results from separate arithmetic units through forwarding buses to store units, thereby resolving the time loss while maintaining the simplicity and speed benefits of specialized units.
2Device complexity
If distinct load/store units and arithmetic/logical units are separated, then the units may be simpler and faster, but there is still time consumed in the forwarding of results
Solution Approach 1:
By integrating the arithmetic/logical unit into the store unit, the patent creates an execution unit that performs both functions. This maintains structural simplicity within each unit while eliminating the inter-unit forwarding delay, as the arithmetic operation and store operation occur within the same unit.
3Loss of time
If the store unit performs both store operations and arithmetic/logical operations, then the time required for processing instructions is reduced by avoiding result forwarding delay, but the device complexity increases
Solution Approach 1:
The store unit is designed with multi-functionality, capable of performing both store operations and arithmetic/logical operations. This universal design allows the unit to handle multiple instruction types without requiring separate specialized units, thereby reducing overall processing time while managing complexity through a consolidated structure.
Data Source
AI summary
A superscalar pipelined microprocessor includes a register set defined by an instruction set architecture of the microprocessor, execution units, and a store unit, coupled to the cache memory and distinct from the other execution units of the microprocessor. The store unit comprises an ALU. The store unit receives an instruction that specifies a source register of the register set and an operation to be performed on a source operand to generate a result. The store unit reads the source operand from the source register. The ALU performs the operation on the source operand to generate the result, rather than forwarding the source operand to any of the other execution units of the microprocessor to perform the operation on the source operand to generate the result. The store unit operatively writes the result to the cache memory.