Strain Engineering Layer in Through-Substrate Vias
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The formation of through-substrate vias (TSVs) in electronic devices creates a local stress field that adversely affects the performance of nearby devices, particularly long channel transistors and those with thick gate oxide/dielectric layers, due to mismatch in thermal expansion coefficients between the substrate and conductive material.
Innovation Solution
Incorporating a strain engineering layer over the sidewall of the TSV, which can offset the intrinsic stress state of the via, reducing or manipulating the TSV stress field to minimize its impact on adjacent devices, thereby enhancing device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If through-substrate vias are formed to enable 3D stacking and increased device integration, then device packaging density is improved, but stress fields are generated that adversely affect the performance of nearby devices
Solution Approach 1:
A strain engineering layer is introduced as an intermediary between the TSV conductive material and the surrounding substrate. This layer mediates the stress field by having different thermal expansion properties than the conductive material, thereby compensating for the stress-induced strain and protecting nearby devices from performance degradation
Solution Approach 2:
The thermal expansion coefficient parameter is changed by introducing a strain engineering layer with specific material properties. This layer is engineered to have thermal expansion characteristics that counterbalance the stress field generated by the TSV conductive material, thereby transforming the stress profile to minimize impact on adjacent devices
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The strain engineering layer effectively mitigates the stress-induced effects on devices near TSVs, allowing for increased device packaging density and improved performance by neutralizing or manipulating the stress field, depending on the device type and position relative to the TSV.
Implementation Method 1
mismatch in thermal expansion coefficients between the substrate and conductive material
Data Source
AI summary
Through-substrate vias (TSVs) include a strain engineering layer configured to minimize or otherwise control local stress fields. The strain engineering layer can be separate from and in addition to a TSV sidewall isolation layer that is deposited along the via sidewall surface for the purpose of electric isolation. For instance, the strain engineering layer can be a partial depth layer that extends over only a portion of the TSV sidewall.