Strain-Generating Liner for Integrated Circuit Gate Formation
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Solution Overview
Problem
The uppermost portions of strain-generating layers in integrated circuits, extending alongside gates, do not contribute meaningfully to channel strain and can cause gate deformation and fill issues during gate replacement, leading to increased gate resistance and contact alignment problems.
Innovation Solution
Selectively removing the uppermost portions of the strain-generating layer from alongside the device gates and forming a modified strain-generating liner that extends only along the source/drain features and bottom portions of the gates, allowing for improved channel strain without deforming the gates or causing fill defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If strain-generating layers are extended alongside gates to improve channel strain, then carrier mobility is improved, but gate deformation and fill issues occur during gate replacement
Solution Approach 1:
The strain-generating layer is segmented into two distinct regions: a first region extending alongside the source/drain features that provides channel strain, and a second region that is selectively removed alongside the gate. This segmentation allows the strain function to be preserved while eliminating the harmful uppermost portions that cause gate deformation and fill issues during gate replacement.
Solution Approach 2:
The uppermost portions of the strain-generating layer are selectively removed (taken out) from alongside the device gates. This extraction eliminates the source of gate deformation and fill defects while preserving the strain-generating functionality in the lower regions that remain alongside the source/drain features.
2Manufacturing precision
If strain-generating layers are removed alongside gates to prevent gate deformation, then manufacturing precision is improved, but channel strain is reduced
Solution Approach 1:
Different regions of the strain-generating layer are assigned different functions: the first region alongside source/drain features maintains full height to provide channel strain for improved carrier mobility, while the second region alongside the gate is selectively removed to prevent gate deformation. This local differentiation resolves the contradiction by optimizing each region for its specific purpose.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances electrical performance by reducing gate resistance and ensuring proper gate formation, while maintaining channel strain for improved carrier mobility and switching speed.
Implementation Method 1
strain-generating layers are formed to apply stress to portions of the devices and thereby improve the flow of charge carriers through the channel regions of the devices
Data Source
AI summary
Examples of an integrated circuit with a strain-generating liner and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a substrate, a fin extending from the substrate, and a gate disposed on the fin. The gate has a bottom portion disposed towards the fin and a top portion disposed on the bottom portion. A liner is disposed on a side surface of the bottom portion of the gate such that the top portion of the gate is free of the liner. In some such examples, the liner is configured to produce a channel strain.