Strain-Induced SOT Memory Cell for Low Switching Current
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Solution Overview
Problem
Spin-transfer torque random access memory (STT-MRAM) devices face reliability and endurance issues due to high writing current density and shared read/write paths, while conventional Spin-Orbit-Torque (SOT)-MRAM has high switching currents and power consumption.
Innovation Solution
A memory cell design incorporating a substrate with a cell selector unit, a magnetic tunnel junction (MTJ) element, and a spin-orbit-torque (SOT) layer, where a strain-induced layer is coupled to a digital line to induce strain on the SOT layer, reducing magnetic anisotropy and switching current during write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high writing current density is used in STT-MRAM, then switching capability is improved, but reliability and endurance deteriorate due to rapid aging of the tunnel barrier
Solution Approach 1:
The patent replaces the direct spin transfer torque mechanism (which requires high current through the tunnel barrier) with a strain-induced mechanism. A piezoelectric layer converts electrical signals to mechanical strain, which then modifies the magnetic anisotropy of the free layer, enabling switching without high current density through the MTJ, thus preserving reliability while maintaining switching capability.
Solution Approach 2:
The patent introduces a piezoelectric layer as an intermediary between the electrical write signal and the magnetic free layer. This intermediary converts electrical energy to mechanical strain, which then acts on the magnetic layer to induce switching. This mediation avoids the direct high current density path through the tunnel barrier that causes degradation.
2Device complexity
If shared read and write paths are used in STT-MRAM, then device complexity is reduced, but erroneous writing occurs during read operations
Solution Approach 1:
The patent applies different mechanisms to different operations: strain-induced switching for write operations and spin transfer torque for read operations. The piezoelectric layer is activated only during write operations, while the read path remains separate through the MTJ tunnel barrier, ensuring read operations do not cause erroneous writing.
3Reliability
If conventional SOT-MRAM is used with separate read and write paths, then erroneous writing is prevented, but switching current remains very high and power consumption increases
Solution Approach 1:
The patent changes the physical parameter used for switching from direct current-driven spin transfer torque to strain-induced magnetic anisotropy modification. By using the piezoelectric effect to induce strain, the switching current density is significantly reduced compared to conventional SOT-MRAM, while maintaining separate read/write paths for reliability.
4Speed
If high current density is applied to switch MTJ magnetization, then switching speed is improved, but tunnel barrier aging accelerates
Solution Approach 1:
The patent substitutes the electrical current-driven switching mechanism with a mechanically-induced strain mechanism. The piezoelectric layer generates mechanical strain in response to electrical signals, which then modifies the magnetic anisotropy energy landscape to enable switching. This mechanical substitution eliminates the need for high current density through the tunnel barrier, preserving its lifetime while maintaining switching speed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables energy-efficient and reliable magnetic memory cells with low switching current, distinct read/write paths to prevent errors, and compatibility with CMOS logic processing, enhancing endurance and reliability of the MTJ elements.
Implementation Method 1
When the DL is activated, an electric field applied to the strain induced layer induces a strain on the SOT layer which reduces magnetic anisotropy of the free layer that is in direct contact with the SOT layer
Data Source
AI summary
Memory cells and methods for forming a memory cell are disclosed. The memory cell includes a substrate defined with a memory cell region. A cell selector unit is defined on the substrate. The cell selector unit includes at least one select transistor. A storage element which includes a magnetic tunnel junction (MTJ) element is coupled to the selector unit. The MTJ element includes a free layer, a fixed layer and a tunnel barrier sandwiched between the fixed and free layers. A spin-orbit-torque (SOT) layer is coupled to the selector unit and is in direct contact with the free layer. A strain induced layer is coupled to a digital line (DL) and is in direct contact with the SOT layer. When the DL is activated, an electric field applied to the strain induced layer induces a strain on the SOT layer.