Strain-Inducing Conductive Layer for FinFET Channel Mobility
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Solution Overview
Problem
The semiconductor industry faces challenges in scaling down FinFET devices due to physical limits of IC materials and high costs and complexity in fabricating dual metal gate devices, with existing channel strain techniques not providing satisfactory results for improved electron and hole mobility.
Innovation Solution
A substrate with strained channel regions, including tensile and compression-strained channels, is fabricated using epitaxial silicon and silicon germanium growths, with a gate structure comprising high-k dielectric and metal layers to induce strain and enhance mobility, and a method involving heat treatment and capping layers to impart strain to the channel regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If channel strain techniques are applied to improve electron and hole mobility, then device performance is improved, but the level of channel strain obtained is not satisfactory
Solution Approach 1:
The patent changes the physical and chemical parameters of the gate structure by introducing a strain-inducing conductive layer with specific lattice mismatch characteristics. This layer is positioned between two other conductive layers to create controlled tensile or compressive strain in the channel region, directly addressing the insufficient strain level achieved by conventional methods
Solution Approach 2:
The gate structure employs a composite multi-layer configuration consisting of a first conductive layer, a strain-inducing conductive layer with different lattice constant, and a second conductive layer. This composite structure enables simultaneous achievement of electrical conductivity and mechanical strain induction in the channel region
2Reliability
If dual metal gate FinFET devices are fabricated to improve device performance, then device performance is improved, but fabrication costs and process complexity increase
Solution Approach 1:
The strain-inducing conductive layer serves multiple functions simultaneously: it acts as part of the gate electrode structure for electrical control and as a strain induction mechanism for mobility enhancement. This multi-functionality eliminates the need for separate strain induction processes or additional metal gate layers, reducing fabrication complexity while maintaining device performance improvements
3Productivity
If FinFET device dimensions are reduced to increase device density, then device density is improved, but physical limits of IC materials are encountered
Solution Approach 1:
The patent changes the mechanical strain parameters in the channel region through the strain-inducing conductive layer, which compensates for the performance degradation caused by dimensional scaling. By controlling the lattice mismatch and layer thickness, adequate strain levels are maintained even as device dimensions are reduced to increase density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively increases electron and hole mobility, reduces threshold voltage, and improves device efficiency by strategically inducing tensile and compressive strain in channel regions, overcoming limitations in existing technologies.
Implementation Method 1
a strain-inducing conductive layer disposed over the first conductive layer, and having the characteristic with a second value, wherein the second value is different from the first value
Implementation Method 2
imparting strain to the channel region, including performing a heat treatment on the gate structure
Implementation Method 3
imparting strain to the channel region, including performing a heat treatment on the gate structure
Implementation Method 4
fabricated using epitaxial silicon and silicon germanium growths
Data Source
AI summary
An apparatus includes a substrate having a strained channel region, a dielectric layer over the channel region, first and second conductive layers over the dielectric layer having a characteristic with a first value, and a strain-inducing conductive layer between the conductive layers having the characteristic with a second value different from the first value. A different aspect involves an apparatus that includes a substrate, first and second projections extending from the substrate, the first projection having a tensile-strained first channel region and the second projection having a compression-strained second channel region, and first and second gate structures engaging the first and second projections, respectively. The first gate structure includes a dielectric layer, first and second conductive layers over the dielectric layer, and a strain-inducing conductive layer between the conductive layers. The second gate structure includes a high-k dielectric layer adjacent the second channel region, and a metal layer.