Strain-Inducing Layer for Memory Channel Conductivity
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Solution Overview
Problem
In three-dimensional flash memory technology, the conductive channel often has medium to low mobility of channel carriers due to deposition on non-templated surfaces, leading to low conductivity, which can be improved by increasing grain size or using higher mobility materials but results in integration complexity and poor gate oxide/channel interface properties.
Innovation Solution
Incorporating a strain-inducing layer with a higher coefficient of thermal expansion than the conductive channel, positioned between the insulating material core and the conductive channel, to induce tensile strain, thereby increasing the mobility of channel carriers and enhancing electrical conductivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the conductive channel is deposited on non-templated surfaces, then the manufacturing process is simpler, but the channel carrier mobility is medium to low resulting in low conductivity
Solution Approach 1:
The patent changes the physical state and structural parameters of the conductive channel by introducing a strain-inducing layer that creates tensile strain. This strain modifies the crystal structure and electron transport properties of the channel material, transforming it from a low-mobility deposited layer to a high-mobility strained channel that achieves conductivity comparable to bulk materials while maintaining the simple non-templated deposition process
Solution Approach 2:
The patent creates a composite structure by integrating the conductive channel with a strain-inducing layer. This composite system combines the ease of deposition of the channel material with the strain-inducing properties of the adjacent layer, achieving both manufacturing simplicity and high conductivity through the synergistic interaction between the two materials
2Reliability
If grain size is increased or higher mobility materials are used, then channel conductivity is improved, but integration complexity increases and gate oxide/channel interface properties deteriorate
Solution Approach 1:
The patent applies local quality by introducing strain only in the specific region where the conductive channel is located, rather than modifying the entire device structure. The strain-inducing layer is positioned locally adjacent to the channel, creating tensile strain precisely where needed to enhance carrier mobility without affecting other device components or increasing overall integration complexity
Solution Approach 2:
The patent replaces the mechanical approach of increasing grain size or using different materials with a stress/strain-based mechanism. Instead of physically restructuring the channel or substituting materials, the invention uses tensile strain induced by the adjacent layer to modify electron transport properties, achieving high conductivity through mechanical stress rather than material composition changes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The strain-inducing layer increases channel carrier mobility by up to 15% or more, improving the conductivity of the conductive channel, which addresses the limitations of existing technologies by enhancing electrical conductivity without increasing integration complexity.
Implementation Method 1
the strain-inducing layer has a higher coefficient of thermal expansion (CTE) than the conductive channel
Data Source
AI summary
A memory structure can include a conductive channel, a charge storage structure adjacent to the conductive channel, and a strain-inducing layer adjacent to the conductive channel on a side opposite the charge storage structure. The strain-inducing layer can have a higher coefficient of thermal expansion (CTE) than the conductive channel.