Strain Layer Width Matching for Transistor Performance
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Solution Overview
Problem
In semiconductor device fabrication, transistors with identical channel lengths but varying source or drain region widths experience uneven compression stresses due to different etching profiles, leading to inconsistent performance and reduced reliability.
Innovation Solution
The implementation of strain layers with controlled widths on either side of the gate structures in the substrate, using semiconductor compound epitaxy layers like SiC or SiGe, to ensure identical strains across all transistors, regardless of their source or drain region widths, thereby maintaining consistent performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If SiGe is filled back in the source or drain region by selective area epitaxy growth process, then the holes in the source or drain region have higher mobility and device performance is enhanced, but different compression stresses are generated in channel regions of transistors with different source or drain widths
Solution Approach 1:
The patent applies local quality by making the strain layer width match the channel width for each transistor type. NMOS transistors have strain layers with a first width corresponding to their channel width, while PMOS transistors have strain layers with a second width corresponding to their channel width. This ensures that each transistor receives uniform and appropriate strain in its channel region, resolving the issue of non-uniform compression stresses while maintaining enhanced device performance.
2Ease of manufacture
If etching process is used to remove predetermined portion of substrate, then source or drain regions can be formed, but loading effect causes larger areas to be etched faster and more deeply resulting in oblique profiles and uneven strains
Solution Approach 1:
The patent addresses the etching loading effect by implementing local quality through width-matched strain layers. Each strain layer's width is specifically designed to match its corresponding transistor's channel width, ensuring that even when transistors have different source or drain widths and experience different etching rates, the final strain distribution in the channel regions remains uniform and controlled.
3Adaptability or versatility
If transistors have identical channel lengths but different source or drain region widths, then design requirements are met, but inconsistent performance and reduced reliability result from different strains in channel regions
Solution Approach 1:
The patent resolves the contradiction between design flexibility and performance consistency by applying local quality. The strain layer widths are locally optimized to match each transistor's channel width, allowing transistors to have different source or drain widths for various design requirements while ensuring that each transistor's channel region receives uniform and appropriate strain, thereby maintaining consistent performance and reliability across all devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures that all transistors have identical strains, enhancing the reliability and performance of the semiconductor device while avoiding the loading effects during the etching process, thus addressing the issue of inconsistent performance caused by varying source or drain region widths.
Implementation Method 1
since Ge has a larger atom volume and applies a compression stress on the channel, the holes in the source or drain region mainly constituted by SiGe may have a higher mobility
Implementation Method 2
Each of the tensile stress layers includes a first semiconductor compound epitaxy layer, and each of the compression stress layers includes a second semiconductor compound epitaxy layer
Data Source
AI summary
A semiconductor device including transistors and strain layers is provided. Each transistor includes a source region and a drain region on a substrate and a gate structure on a channel region between the source region and the drain region. Lengths of the channel regions of these transistors are the same, but at least one source or drain region has a width along a channel length direction and the width is different from widths of other source or drain regions. The strain layers include first and second strain layers embedded separately at two sides of each gate structure in the substrate. A first width of each first strain layer along the channel length direction is the same, and a second width of each second strain layer along the channel length direction is the same.