Strain Measurement Test Module for Transistor Channels
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Solution Overview
Problem
Current strain measurement techniques for transistor channels face challenges in achieving accurate and reproducible measurements due to sample thickness issues, leading to stress relaxation and signal degradation, which affects the comparison of strain across different samples and manufacturing processes.
Innovation Solution
A test structure comprising PMOS and NMOS transistor regions with optimized dimensions and materials, such as SiGe and SiC source and drains, is developed to facilitate precise strain measurements using techniques like NBD, CBED, and GPA, with an unstressed reference region for improved accuracy and reproducibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional strain measurement techniques (NBD, CBED, GPA) are used on transistor channels, then strain can be measured, but sample thickness variations cause stress relaxation and signal degradation, reducing measurement precision and reproducibility
Solution Approach 1:
The test structure is divided into distinct functional regions: stressed transistor regions (PMOS and NMOS with different channel lengths) and an unstressed reference region. This segmentation allows separate measurement zones that can be independently optimized for their specific functions, enabling precise strain measurements by comparing stressed channels against an unstressed reference on the same wafer.
Solution Approach 2:
The invention varies channel length as a critical parameter to create transistors with different strain characteristics. By fabricating transistors with multiple channel lengths (e.g., 50nm, 100nm, 200nm) on the same wafer, the test structure enables study of strain effects across different dimensional parameters while maintaining consistent fabrication conditions, thereby improving measurement reliability.
2Adaptability or versatility
If multiple transistor types with different channel lengths are fabricated to study strain effects, then comprehensive strain data can be obtained, but variations in sample thickness and fabrication conditions introduce inconsistencies that reduce manufacturing precision
Solution Approach 1:
The test structure serves multiple functions within a single integrated design: it provides stressed regions for both PMOS and NMOS transistors, includes multiple channel length variations, and incorporates an unstressed reference region. This multi-functional design enables comprehensive strain characterization across different transistor types and dimensions while maintaining consistent fabrication conditions, thereby achieving both versatility and precision.
Solution Approach 2:
All transistor regions and the reference region are fabricated on the same wafer under identical fabrication conditions, creating an equipotential baseline for comparison. This ensures that any measured strain differences are due to the intended structural variations (channel length, transistor type) rather than fabrication variability, thereby improving manufacturing precision and measurement consistency.
3Productivity
If stressed regions are used to enhance carrier mobility, then transistor performance improves, but accurate measurement of the strain tensor becomes difficult due to stress relaxation in thin samples
Solution Approach 1:
The unstressed reference region acts as an intermediary for calibration and comparison. By providing an unstressed baseline on the same wafer, it enables accurate determination of strain in the stressed transistor regions through comparison, effectively mediating the measurement process and compensating for stress relaxation effects in thin samples.
Solution Approach 2:
The test structure is designed with predetermined channel lengths and transistor types before fabrication, with the unstressed reference region already in place. This preliminary design allows for planned measurement protocols that compare stressed regions against the reference, enabling accurate strain tensor measurement before stress relaxation can occur during subsequent processing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed test structure enables accurate and reproducible strain measurements, reducing variations and improving the calibration of strain modeling tools, allowing for better correlation of transistor performance with channel strain, thereby enhancing manufacturing control and optimization.
Implementation Method 1
Since germanium is a bigger atom than silicon, compressive strain is applied to the channel region 1002 under the transistor gate 1006
Implementation Method 2
Stress enhancement techniques such as the deposition of overlying highly stressed films may be used to apply additional stress to the channel region
Implementation Method 3
in nano-beam diffraction (NBD) a collimated electron beam is scattered off the atoms in the sample 4006 forming a diffractogram such as in FIG. 5 after passing though objective lens 4004
Implementation Method 4
in convergent beam electron diffraction (CBED), a convergent beam of electrons 5010 is scattered off the atoms in the sample 5006 forming a diffractogram of disks as shown in FIG. 7
Implementation Method 5
A high-resolution, high-angle annular dark field scanning transmission electron microscopy (HAADF-STEM) image of a PMOS transistor with SiGe source and drains is shown in FIG. 3
Implementation Method 6
The diffractogram in FIG. 9 is a Fourier transformed image of the high resolution HAADF-STEM image in FIG. 8. Information regarding strain in various portions of the high-resolution HAADF-STEM image is contained in the blurring of the points such as g0 and g1 in FIG. 9
Data Source
AI summary
A test structure for measuring strain in the channel of transistors. A method of correlating transistor performance with channel strain.