Strain-Relaxed Buffer Layer for MOS Transistor Stress Management
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Solution Overview
Problem
The scaling down of MOS transistors leads to short-channel effects and reduced current flow, compromising the performance and reliability of semiconductor devices, as narrower channels increase the likelihood of defective performance characteristics.
Innovation Solution
A semiconductor device is manufactured with a strain-relaxed buffer layer and channel layers of varying lattice constants, where the first channel layer has a lattice constant less than the buffer layer and the second channel layer has a lattice constant greater than the buffer layer, inducing tensile or compressive stress to enhance charge carrier mobility in NMOS and PMOS transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the channel width and length of MOS transistors are reduced to scale down device size, then the overall device size is reduced, but short-channel effects occur and current flow decreases, compromising performance and reliability
Solution Approach 1:
The patent applies different lattice constants to different channel layers (first channel layer with lattice constant less than buffer layer, second channel layer with lattice constant greater than buffer layer) to create localized stress conditions. This allows NMOS and PMOS transistors to experience different stress states optimized for their specific carrier types, improving performance without requiring larger device dimensions.
Solution Approach 2:
The patent changes the physical parameter of lattice constant across different channel layers to induce stress. By varying the lattice constant relative to the buffer layer, tensile or compressive stress is generated in the channel regions, which modifies charge carrier mobility and compensates for the negative effects of channel scaling.
2Volume of moving object
If the channel width is reduced to decrease device size, then the device becomes more compact, but the amount of current flowing through the channel decreases, compromising transistor performance
Solution Approach 1:
Different channel layers are assigned different lattice constants to create localized stress fields. The first channel layer (with smaller lattice constant) induces compressive stress suitable for NMOS, while the second channel layer (with larger lattice constant) induces tensile stress suitable for PMOS. This localized stress application enhances current flow in narrow channels without increasing device size.
Solution Approach 2:
The patent employs a composite structure with multiple channel layers made of materials having different lattice constants. This composite approach allows simultaneous optimization of different transistor types (NMOS and PMOS) within the same device, enhancing overall current flow capability while maintaining compact dimensions.
3Reliability
If channel layers with varying lattice constants are used to induce stress and improve carrier mobility, then charge carrier mobility is enhanced, but stacking faults and dislocation defects may occur due to lattice mismatch
Solution Approach 1:
The channel structure is segmented into multiple layers with different lattice constants rather than using a single continuous layer. This segmentation allows stress to be applied in a controlled manner through discrete layers, reducing the accumulation of lattice mismatch stress that would otherwise cause stacking faults and dislocations.
Solution Approach 2:
The buffer layer acts as an intermediary between the substrate and the channel layers with varying lattice constants. This intermediate layer helps to Gradually transition the lattice structure, reducing abrupt mismatches and minimizing the generation of stacking faults and dislocation defects while still allowing stress to be transmitted to the channel regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces stacking faults and dislocation defects, improving the mobility of charge carriers and enhancing the performance and reliability of semiconductor devices by managing stress within the channel regions.
Implementation Method 1
a lattice constant of material constituting the first channel layer is less than a lattice constant of material constituting the strain-relaxed buffer layer, and a lattice constant of material constituting the second channel layer is greater than said lattice constant of the material constituting the strain-relaxed buffer layer
Data Source
AI summary
A semiconductor device includes a substrate, a strain-relaxed buffer layer on the substrate, at least one well in the strain-relaxed buffer layer, a first channel layer on the strain-relaxed buffer layer, and a second channel layer on the well. A lattice constant of material constituting the first well is less than a lattice constant of the material constituting the strain-relaxed buffer layer, but a lattice constant of material constituting the second well is greater than the lattice constant of the material constituting the strain-relaxed buffer layer.