Localized Strain Relaxed SiGe Buffer Layer
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Solution Overview
Problem
Threading dislocations in SiGe buffer layers on lattice-mismatched substrates lead to rough surfaces, partial strain relaxation, and high dislocation density, negatively impacting the growth and quality of semiconductor devices.
Innovation Solution
A method involving the formation of a multilayered structure with a tensile strained dielectric layer on a semiconductor substrate, inducing compressive strain and annealing to propagate and immobilize misfit and threading dislocations, resulting in a thin, strain-relaxed SiGe buffer layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If a thick SiGe buffer layer is used to achieve complete strain relaxation, then the degree of strain relaxation is improved, but the surface roughness increases and threading dislocation density remains high
Solution Approach 1:
The buffer layer is divided into multiple thinner SiGe layers separated by Si interlayer regions. Each SiGe layer is thin enough to remain strain-relaxed without forming excessive threading dislocations, while the Si interlayers provide spacing that prevents dislocation propagation between layers. This segmentation achieves complete strain relaxation with smooth surfaces and low dislocation density.
Solution Approach 2:
Silicon interlayer regions are introduced as intermediary layers between SiGe buffer layers. These Si interlayers act as mediators that block the propagation of threading dislocations from one SiGe layer to another, while still allowing each individual SiGe layer to be fully strain-relaxed. This results in a multi-layer structure with overall strain relaxation but without the surface roughness and high dislocation density problems of thick single layers.
2Stability of the object's composition
If a thick SiGe buffer layer is used to achieve complete strain relaxation, then the degree of strain relaxation is improved, but threading dislocation density increases
Solution Approach 1:
The buffer layer is divided into multiple thinner SiGe layers separated by Si interlayer regions. Each SiGe layer is thin enough to achieve complete strain relaxation without generating excessive threading dislocations, and the Si interlayers block dislocation propagation between layers. This segmentation achieves complete strain relaxation with low threading dislocation density.
Solution Approach 2:
Silicon interlayer regions are introduced as intermediary layers between SiGe buffer layers. These Si interlayers act as barriers that prevent threading dislocations from propagating through the entire buffer structure, while allowing each individual SiGe layer to be fully strain-relaxed. This results in complete strain relaxation with reduced threading dislocation density.
3Shape
If a thin SiGe buffer layer is used to maintain surface smoothness, then surface roughness is improved, but strain relaxation is incomplete
Solution Approach 1:
The buffer structure is segmented into multiple thin SiGe layers, each thin enough to maintain surface smoothness and avoid excessive dislocation formation. By stacking multiple such layers with Si interlayers in between, the cumulative effect achieves complete strain relaxation while each individual layer remains thin and smooth, solving both contradictions simultaneously.
4Ease of manufacture
If conventional SiGe buffer layers are used, then device fabrication is simplified, but surface roughness and dislocation density adversely impact device quality
Solution Approach 1:
The buffer layer is segmented into multiple thin SiGe layers with Si interlayers, which can be deposited using standard epitaxial techniques. This segmented structure maintains compatibility with conventional fabrication processes while dramatically improving surface smoothness and reducing dislocation density, thereby enhancing device quality without sacrificing manufacturing ease.
Solution Approach 2:
The buffer structure uses a composite multi-layer design combining SiGe and Si layers. This composite structure leverages the strain-relaxation properties of SiGe while using Si interlayers to block dislocation propagation and maintain surface quality. The result is a buffer structure that improves device quality while remaining compatible with standard semiconductor fabrication processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces threading dislocation density, enhances strain relaxation, and produces a smooth surface, improving the quality of subsequent semiconductor layers and devices.
Implementation Method 1
depositing a tensile strained dielectric layer on a top surface of the semiconductor layer to induce a compressive strain in the semiconductor layer
Implementation Method 2
annealing the multilayered structure to cause the misfit dislocations and associated threading dislocations to propagate within the semiconductor layer
Data Source
AI summary
A method includes forming a multilayered structure by providing a substrate having a semiconductor layer disposed on a top surface thereof, the semiconductor layer containing misfit dislocations and associated threading dislocations. The method further includes depositing a tensile strained dielectric layer on a top surface of the semiconductor layer to induce a compressive strain in the semiconductor layer and annealing the multilayered structure to cause the misfit dislocations and associated threading dislocations to propagate within the semiconductor layer. The method further immobilizes the propagating misfit dislocations and associated threading dislocations in a predetermined portion of the semiconductor layer. A multilayered structure formed by the method is disclosed wherein a semiconductor layer contains misfit dislocations and associated threading dislocations that are immobilized within a predetermined portion of the semiconductor layer, where other portions of the semiconductor layer surrounding the predetermined portion are locally strain relaxed portions.