Strain Transformation in Biaxially Strained SOI Substrates
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Solution Overview
Problem
Current strain-inducing mechanisms in integrated circuits, such as local strain engineering, face challenges in achieving sufficient strain in channel regions of transistors due to reduced device dimensions, leading to performance imbalances between N-channel and P-channel transistors and increased production costs.
Innovation Solution
The use of globally strained silicon-based semiconductor materials with trench isolation structures to modify strain components within active regions by adjusting the aspect ratio of these regions, allowing for tailored strain distribution to enhance both N-channel and P-channel transistor performance without additional strain-inducing mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If local strain engineering techniques are used to enhance transistor performance, then charge carrier mobility can be improved, but device complexity and production costs increase
Solution Approach 1:
The patent changes the strain parameter from local to global by using biaxially strained SOI substrates. The substrate is pre-strained before transistor fabrication, eliminating the need for complex local strain-inducing structures. This global parameter change maintains high charge carrier mobility while simplifying the overall device structure and reducing production complexity.
Solution Approach 2:
The strain is applied preliminarily to the SOI substrate before the transistor fabrication process begins. By pre-straining the substrate, the patent eliminates the need for subsequent complex strain-inducing steps during manufacturing, thereby reducing device complexity while maintaining performance benefits.
2Speed
If channel length is reduced to increase operating speed, then transistor performance improves, but short channel effects and leakage currents increase
Solution Approach 1:
The patent changes the physical state of the channel material by introducing biaxial strain, which modifies the band structure and increases charge carrier mobility. This parameter change allows for higher operating speeds even at reduced channel lengths, while the strained structure helps maintain channel controllability by enhancing the electric field effect.
3Speed
If gate dielectric thickness is reduced to maintain performance at smaller nodes, then operating speed improves, but leakage currents increase
Solution Approach 1:
The patent changes the mobility parameter of charge carriers through biaxial strain, which compensates for the performance loss that would normally require further gate dielectric thinning. By improving mobility through strain rather than further reducing dielectric thickness, the patent maintains operating speed without exacerbating leakage current issues.
4Ease of manufacture
If a single global strain component is used for both N-channel and P-channel transistors, then manufacturing simplicity is maintained, but performance optimization for both transistor types becomes difficult
Solution Approach 1:
The patent applies local quality by creating different strain conditions in different regions of the same globally strained substrate. Through selective device design and positioning, N-channel and P-channel transistors experience different effective strain components, allowing both types to be optimized for their respective performance requirements while using a single global strain approach.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables superior performance of both N-channel and P-channel transistors using a single global strain component, reducing production costs and avoiding complex local strain engineering techniques, while maintaining or improving transistor performance across different technology nodes.
Implementation Method 1
the silicon-containing semiconductor layer has a biaxial strain of a first type
Implementation Method 2
forming a trench isolation structure in the silicon-containing semiconductor layer so as to define an active region having a surface region with a biaxial strain of a second type that differs from the first type
Data Source
AI summary
In advanced SOI devices, a high tensile strain component may be achieved on the basis of a globally strained semiconductor layer, while at the same time a certain compressive strain may be induced in P-channel transistors by appropriately selecting a height-to-length aspect ratio of the corresponding active regions. It has been recognized that the finally obtained strain distribution in the active regions is strongly dependent on the aspect ratio of the active regions. Thus, by selecting a moderately low height-to-length aspect ratio for N-channel transistors, a significant fraction of the initial tensile strain component may be preserved. On the other hand, a moderately high height-to-length aspect ratio for the P-channel transistor may result in a compressive strain component in a central surface region of the active region.