Strain-Enhanced Transistor Layouts With Dummy Gate Fingers
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Solution Overview
Problem
Conventional strained transistor layouts face incomplete epitaxial regions and inadequate channel stress due to the presence of shallow trench isolation structures, which hinder the effective formation of stress-inducing epitaxial regions.
Innovation Solution
The use of computer-aided design tools to optimize the design of strain-enhanced transistors by adjusting the size and layout of stress-inducing epitaxial regions, including the formation of dummy gate fingers, to ensure adequate stress is produced under the channel regions, while maintaining the same well region width and gate finger count for similar transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If shallow trench isolation structures are used to surround well regions, then field oxide formation is achieved, but epitaxial growth is inhibited near the edges due to silicon starvation
Solution Approach 1:
The patent applies preliminary action by forming dummy gate fingers before epitaxial growth to pre-establish the geometric boundaries that will guide complete epitaxial region formation. These dummy structures are positioned to ensure that epitaxial material can grow uniformly to the desired extent without being starved by the isolation structures, thereby resolving the contradiction between field oxide formation and epitaxial completeness.
Solution Approach 2:
The dummy gate fingers serve as intermediary structures that mediate between the shallow trench isolation structures and the epitaxial growth regions. They act as geometric guides that prevent silicon starvation at the edges by defining clear boundaries for epitaxial material deposition, ensuring complete epitaxial regions while maintaining the field oxide isolation structures.
2Device complexity
If regular pattern of gate fingers is formed within well region, then transistor structure is established, but inadequate channel stress occurs due to incomplete epitaxial regions near isolation structures
Solution Approach 1:
The patent applies local quality by adding dummy gate fingers specifically at the outer edges of the transistor structure where epitaxial incompleteness occurs. These localized dummy structures create additional epitaxial regions that generate the necessary channel stress only where needed, without altering the main transistor structure or requiring changes to the well region width or gate finger count.
3Reliability
If transistor strength is adjusted by changing well region width or gate finger count, then transistor performance is optimized, but other similar transistors must also be changed
Solution Approach 1:
The patent applies segmentation by introducing dummy gate fingers as separate, independent structures from the main transistor gate fingers. This segmentation allows individual transistors to be tuned by selectively adding or removing dummy gate fingers without affecting the core transistor structure or requiring changes to similar transistors, enabling localized performance optimization while maintaining consistency across the device family.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for localized adjustment of transistor strength by optimizing the spacing between gate fingers and epitaxial regions, ensuring consistent and enhanced channel stress, thereby improving transistor performance without altering the well region width or gate finger count.
Implementation Method 1
Epitaxial regions may be formed within the well to produce compressive or tensile stress in the transistor channel regions that lie under the gate fingers
Data Source
AI summary
A transistor may include a semiconductor region such as a rectangular doped silicon well. Gate fingers may overlap the silicon well. The gate fingers may be formed from polysilicon and may be spaced apart from each other along the length of the well by a fixed gate-to-gate spacing. The edges of the well may be surrounded by field oxide. Epitaxial regions may be formed in the well to produce compressive or tensile stress in channel regions that lie under the gate fingers. The epitaxial regions may form source-drain terminals. The edges of the field oxide may be separated from the nearest gate finger edges by a distance that is adjusted automatically with a computer-aided-design tool and that may be larger than the gate-to-gate spacing. Dummy gate finger structures may be provided to ensure desired levels of stress are produced.