Strained Channel Transistor Using Semiconductor Alloy
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Solution Overview
Problem
Current strain engineering techniques for transistors, such as using strained silicon/germanium layers in drain and source regions, do not fully optimize channel region characteristics, leading to limitations in charge carrier mobility and transistor performance, especially for advanced node technologies.
Innovation Solution
The technique involves forming a semiconductor alloy in the channel region with specific material compositions that enhance charge carrier mobility by combining strain-inducing mechanisms with tailored material characteristics, such as reduced band gap energy and scattering effects, allowing for flexible adjustment of strain and electrical properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If strain engineering techniques using strained silicon/germanium layers are applied in drain and source regions, then charge carrier mobility is enhanced, but channel region characteristics are not fully optimized, limiting transistor performance
Solution Approach 1:
The patent applies different material compositions to different regions: the channel region receives a semiconductor alloy with specific non-silicon species concentration optimized for charge carrier mobility, while drain and source regions use strained silicon/germanium layers for strain induction. This local differentiation allows each region to have properties tailored to its specific functional requirements.
Solution Approach 2:
The invention uses composite material structures combining silicon with other semiconductor materials (forming semiconductor alloys) in the channel region, and silicon/germanium strained layers in drain/source regions. These composite materials provide both the strain induction mechanism and the tailored electrical characteristics needed for high-performance transistors.
2Speed
If channel length is reduced to increase operating speed, then drive current capability improves, but short channel effects and controllability issues worsen
Solution Approach 1:
The patent changes the material composition parameter in the channel region by introducing semiconductor alloys with controlled non-silicon species concentrations. This material parameter change enhances charge carrier mobility, allowing the transistor to achieve high drive current capability and operating speed even with reduced channel length, while maintaining adequate channel controllability through the optimized material properties.
3Reliability
If strain-inducing mechanisms are combined with tailored material characteristics, then charge carrier mobility is significantly enhanced, but manufacturing process complexity increases
Solution Approach 1:
The patent incorporates the non-silicon species into the channel region during the epitaxial growth process before transistor fabrication is completed. This preliminary action of forming the semiconductor alloy structure early in the manufacturing process allows subsequent strain engineering and device fabrication to proceed using established techniques, thereby enhancing mobility without proportionally increasing overall process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly enhances transistor performance by optimizing channel region conductivity and flexibility, achieving improved drive current capability and scalability while maintaining compatibility with existing manufacturing processes.
Implementation Method 1
compressively strained drain and source regions create strain in the adjacent silicon channel region
Implementation Method 2
Since the natural lattice spacing of silicon/germanium is greater than that of silicon, the epitaxially grown silicon/germanium layer, adopting the lattice spacing of the silicon, is grown under compressive strain
Implementation Method 3
the deep drain and source junctions may be formed on the basis of a silicon/germanium layer that is selectively formed in respective recesses in the PMOS transistor by epitaxial growth techniques
Data Source
AI summary
By forming a semiconductor alloy in a silicon-based active semiconductor region prior to the gate patterning, material characteristics of the semiconductor alloy itself may also be exploited in addition to the strain-inducing effect thereof. Consequently, device performance of advanced field effect transistors may be even further enhanced compared to conventional approaches using a strained semiconductor alloy in the drain and source regions.