Strained Channel Power MOSFET on Metal Substrate
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Solution Overview
Problem
Conventional techniques for manufacturing vertical power devices, such as MOSFETs, face limitations in reducing on-resistance and improving switching speed due to high substrate resistance and channel impedance, which restrict their application in low-voltage applications.
Innovation Solution
The formation of a strained semiconductor channel region over a heterostructure on a metal substrate, using a relaxed silicon-germanium (SiGe) layer with a graded concentration structure, enhances carrier mobility and reduces substrate resistance by incorporating a thin heavily doped drain region on a supportive metal substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional techniques are used to manufacture vertical power devices, then manufacturing simplicity is maintained, but on-resistance and substrate resistance remain high
Solution Approach 1:
The patent employs a composite substrate structure combining semiconductor material (e.g., silicon) with metal material (e.g., copper or aluminum) to create a metal-semiconductor composite substrate. This composite structure leverages the electrical conductivity of metal to reduce substrate resistance while maintaining the semiconductor's functional properties, directly addressing the contradiction between reducing on-resistance and managing device complexity
Solution Approach 2:
The invention introduces localized heavily doped drain regions and strained channel regions at specific locations within the device structure. These localized modifications improve carrier mobility and reduce on-resistance in critical areas without requiring complete restructuring of the entire substrate, thus balancing manufacturing complexity with performance improvement
2Speed
If conventional channel structures are used, then device simplicity is maintained, but carrier mobility and switching speed are limited
Solution Approach 1:
The patent applies strain engineering by introducing mechanical strain into the channel region through misfit dislocation layers and graded concentration structures. This parameter change in the crystal lattice structure enhances carrier mobility by modifying the band structure and reducing effective mass, thereby improving switching speed without fundamentally changing the device architecture
Solution Approach 2:
The invention introduces misfit dislocation layers as intermediary structures between the substrate and the channel region. These intermediary layers serve as transition zones that manage lattice mismatch while facilitating enhanced carrier transport, improving switching speed without requiring direct modification of the entire channel structure
3Manufacturing precision
If heavily doped drain regions are added to reduce substrate resistance, then on-resistance decreases, but device complexity increases
Solution Approach 1:
The patent incorporates heavily doped drain regions during the initial epitaxial growth process rather than adding them as separate post-processing steps. This preliminary action integrates the doping structure into the manufacturing flow, reducing substrate resistance while minimizing the increase in device complexity by combining multiple functions into a single process step
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly improves the performance of power MOSFETs by reducing on-resistance and channel impedance, enhancing carrier mobility, and facilitating better heat dissipation, thereby expanding their application to higher current regions.
Implementation Method 1
The lattice mismatch causes the channel region to be strained and provide higher carrier mobility
Implementation Method 2
a thin heavily doped drain region is disposed on a supportive metal substrate to reduced substrate resistance
Implementation Method 3
facilitating better heat dissipation
Data Source
AI summary
A field effect transistor device having a strained semiconductor channel region overlying a heterostructure-semiconductor on a metal substrate includes a first semiconductor layer overlying a first metal layer. The first semiconductor layer has a first semiconductor material and a second semiconductor material in a relaxed heterostructure and is heavily doped. A second semiconductor layer overlies the first semiconductor layer and has a first semiconductor material and a second semiconductor material in a relaxed heterostructure. The second semiconductor layer is more lightly doped than the first semiconductor layer. A trench extends into the second semiconductor layer and a channel region has a strained layer of the first semiconductor material adjacent a trench sidewall. The strained channel region provides enhanced carrier mobility and improves performance of the field effect transistor.