Strained-Channel Multi-Gate Transistor for Thermal Dissipation
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Solution Overview
Problem
Existing multi-gate transistor structures, while improving scalability and switching speed, still require further enhancement in device performance, particularly in cost-effectiveness and thermal dissipation, which is not adequately addressed by silicon on insulator substrates.
Innovation Solution
A body-tied, strained-channel multi-gate transistor is developed using a semiconductor substrate with a fin structure having a different lattice constant, where a gate dielectric and gate electrode are formed over the fin, allowing for tuned strain through stress from the substrate interface, and the method involves epitaxial growth of SiGe or SiC to create compressive or tensile strain for improved carrier mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If silicon on insulator substrates are used for multi-gate structures, then electrical isolation and noise reduction are improved, but cost increases and thermal dissipation is insufficient
Solution Approach 1:
The patent changes the substrate parameter from silicon on insulator to bulk silicon, altering the thermal and electrical properties to improve thermal dissipation and reduce cost while maintaining acceptable noise performance through body-tied configuration
Solution Approach 2:
The patent copies the beneficial body-tied configuration from planar transistors and applies it to multi-gate structures, achieving improved thermal dissipation and cost-effectiveness while maintaining the noise isolation benefits
2Ease of manufacture
If planar transistor structures are used, then manufacturing is simpler, but device performance and scalability are limited
Solution Approach 1:
The patent transitions from two-dimensional planar structures to three-dimensional multi-gate structures (fin-FET, omega, or nanowire configurations), increasing the gate control surface area and improving device performance while maintaining compatibility with existing manufacturing processes
3Ease of manufacture
If conventional channel structures are used, then manufacturing is easier, but carrier mobility is insufficient
Solution Approach 1:
The patent changes the physical state of the channel by introducing mechanical strain through lattice-mismatched layers, altering the carrier mobility parameter without changing the fundamental manufacturing process flow
Solution Approach 2:
The patent uses composite material structures with different lattice constants (e.g., SiGe or SiC layers on silicon substrate) to generate strain in the channel region, improving carrier mobility while maintaining manufacturing compatibility
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances carrier mobility and reduces noise by leveraging lattice mismatch-induced strain, offering cost savings and improved thermal dissipation compared to traditional silicon on insulator substrates, while maintaining compatibility with existing manufacturing processes.
Implementation Method 1
a semiconductor fin extending from the semiconductor substrate. The fin has a second lattice constant, different from the first lattice constant
Implementation Method 2
the method involves epitaxial growth of SiGe or SiC to create compressive or tensile strain for improved carrier mobility
Data Source
AI summary
A fin-FET or other multi-gate transistor is disclosed. The transistor comprises a semiconductor substrate having a first lattice constant, and a semiconductor fin extending from the semiconductor substrate. The fin has a second lattice constant, different from the first lattice constant, and a top surface and two opposed side surfaces. The transistor also includes a gate dielectric covering at least a portion of the top surface and the two opposed side surfaces, and a gate electrode covering at least a portion of the gate dielectric. The resulting channel has a strain induced therein by the lattice mismatch between the fin and the substrate. This strain can be tuned by selection of the respective materials.