Strained Semiconductor Channel Formation via Selective Epitaxy
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Solution Overview
Problem
Conventional methods for forming strained Si channels in semiconductor devices face issues such as loss and relaxation of the strained Si blanket layer due to high-temperature processes like anneal, which are unavoidable in device fabrication.
Innovation Solution
A method is developed to form a strained semiconductor channel after removing the sacrificial gate, reducing exposure to high-temperature source/drain anneal and minimizing loss by using a sacrificial gate stack structure, selective epitaxial growth, and forming a semiconductor epitaxial layer with a high-K dielectric and metal gate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a strained Si blanket layer is formed before device fabrication, then the strained channel structure is established early, but the layer suffers loss during fabrication steps and relaxes during high-temperature anneal
Solution Approach 1:
The patent forms the strained Si channel layer after device fabrication steps are completed, rather than before. This reverse sequencing prevents the strained layer from being exposed to loss-inducing processes and high-temperature anneal, thereby maintaining strain reliability while avoiding material loss
Solution Approach 2:
The patent extracts the strained Si channel formation step from the pre-fabrication sequence and places it post-fabrication. By separating this critical step from the fabrication process, the strained layer is protected from both material loss and strain relaxation that occur during standard fabrication and annealing
2Reliability
If a strained Si blanket layer is formed before device fabrication, then the strained channel structure is established early, but the strain relaxes during high-temperature anneal for dopant activation
Solution Approach 1:
The patent performs the strained Si channel formation as a preliminary action that occurs after fabrication but before final device completion. This timing ensures the strained layer is created in a controlled manner without subsequent exposure to high-temperature annealing that would cause strain relaxation
Solution Approach 2:
The patent extracts the strained channel formation from the high-temperature processing sequence entirely. By forming the strained layer after all high-temperature annealing steps are completed, the strained structure is protected from thermal degradation while still enabling device functionality
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents strain relaxation and minimizes loss of the strained semiconductor channel by reducing the number of processing steps, ensuring the strained channel remains intact and functional.
Implementation Method 1
tensile strained Si layer structure disposed on a relaxed SiGe layer
Implementation Method 2
the composition of the relaxed SiGe layer is represented by Si1-xGex, wherein x∈[0,1]
Implementation Method 3
forming a semiconductor epitaxial layer by selective semiconductor epitaxial growth in the opening
Data Source
AI summary
A method of forming a strained semiconductor channel, comprising: forming a relaxed SiGe layer on a semiconductor substrate; forming a dielectric layer on the relaxed SiGe layer and forming a sacrificial gate on the dielectric layer, wherein the dielectric layer and the sacrificial gate form a sacrificial gate structure; depositing an interlayer dielectric layer, which is planarized to expose the sacrificial gate; etching to remove the sacrificial gate and the dielectric layer to form an opening; forming a semiconductor epitaxial layer by selective semiconductor epitaxial growth in the opening; depositing a high-K dielectric layer and a metal layer; and removing the high-K dielectric layer and metal layer covering the interlayer dielectric layer by planarizing the deposited metal layer and high-K dielectric layer to form a metal gate. A semiconductor device manufactured by this process is also provided.