Strained Channel Semiconductor Device with High-k Capping Layers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current techniques for forming strained substrate structures in semiconductor devices, such as MOSFETs, fail to produce sufficient stress in the channel region to enhance device performance effectively.
Innovation Solution
A semiconductor device with a metal gate structure that includes a tensile stress HK capping layer in p-channel PMOS and a compressive stress N-WF metal layer in n-channel NMOS, allowing for independent modulation of strain types in p-channel and n-channel regions, which enhances carrier mobility and device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If strained substrate structures are formed using current techniques, then device performance is improved, but sufficient stress in the channel region is not achieved
Solution Approach 1:
The patent applies different stress types (tensile and compressive) to different local regions (p-channel and n-channel) through selectively positioned capping layers. The tensile stress HK capping layer is formed in closer proximity to the p-channel in PMOS, while the compressive stress N-WF metal layer is formed in closer proximity to the n-channel in NMOS, creating locally optimized stress conditions for each channel type.
Solution Approach 2:
The patent changes the stress parameter from uniform to differentiated by introducing capping layers with opposite stress types. The HK capping layer configuration changes the physical state of stress in the channel region, transitioning from insufficient uniform stress to optimized differentiated stress (tensile for PMOS, compressive for NMOS), thereby enhancing carrier mobility and device performance.
2Reliability
If independent modulation of strain types is implemented, then carrier mobility is enhanced, but device structure complexity increases
Solution Approach 1:
The HK capping layer structure serves multiple functions simultaneously: it provides stress modulation for both PMOS and NMOS devices, acts as a dielectric layer, and enables independent strain type control for different channel types. This multi-functionality reduces the need for separate stress-inducing structures for each device type.
Solution Approach 2:
The patent implements local quality by positioning different stress-type capping layers in proximity to specific channel types (tensile near p-channel, compressive near n-channel), allowing independent strain modulation while maintaining a relatively simple overall structure through selective spatial distribution rather than adding complex independent systems.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively induces compressive strain in p-channels and tensile strain in n-channels, improving hole and electron mobility respectively, thereby enhancing overall device performance and reliability.
Implementation Method 1
a tensile stress HK capping layer formed in closer proximity to a p-channel in a PMOS
Implementation Method 2
a compressive stress N-WF metal layer formed on top of the HK layer in closer proximity to an n-channel in an NMOS
Data Source
AI summary
A semiconductor device with a metal gate is disclosed. The device includes a semiconductor substrate including a plurality of source and drain features to form a p-channel and an n-channel. The device also includes a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes a high-k (HK) dielectric layer formed over the semiconductor substrate. A tensile stress HK capping layer is formed on top of the HK dielectric layer in close proximity to the p-channel, and a compressive stress HK N-work function (N-WF) metal layer is formed on top of the HK dielectric layer in close proximity to the n-channel. A stack of metal gate layers is deposited over the capping layers.