Strained Channel Transistor Gate Integrity
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Solution Overview
Problem
Strained channel transistor manufacturing techniques often damage the gate structure, leading to degraded transistor performance due to silicon etching steps, erosion of spacers, and exposure to cleaning solutions, which can result in short-circuiting and malfunction.
Innovation Solution
Forming recessed regions in the substrate before the gate electrode, using a stress-inducing material with a cap layer and silicide regions, and independently controlling the location and size of recessed regions and gate electrodes without dummy spacers to prevent damage and maintain gate structure integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If silicon etching steps are performed to form recessed regions after gate structure formation, then strained channel is achieved, but gate structure damage occurs
Solution Approach 1:
The recessed regions are formed in the substrate before the gate electrode is deposited, rather than after. This preliminary action allows the gate structure to be formed over the already-defined recessed regions, eliminating exposure to damaging etching steps while maintaining the strained channel configuration
Solution Approach 2:
The conventional sequence is inverted: instead of forming gate structure first then creating recessed regions through etching, the recessed regions are created first through selective epitaxial growth, followed by gate structure formation. This reversal eliminates the harmful etching exposure while achieving the same strained channel effect
2Manufacturing precision
If silicon etching steps are performed after spacer formation, then recessed regions are formed, but spacer erosion occurs
Solution Approach 1:
The recessed regions are formed through selective epitaxial growth before spacer deposition, eliminating the need for subsequent etching steps that would erode the spacers. The spacers are then formed to precisely define the gate electrode boundaries without exposure to damaging etchants
3Ease of manufacture
If pre-cleaning with hydrofluoric acid is performed before lattice mismatch material deposition, then cleaning is achieved, but spacer voids form
Solution Approach 1:
The harmful pre-cleaning step with hydrofluoric acid is completely removed from the process sequence. The substrate is prepared through alternative means that do not involve aggressive chemical cleaning, thereby preventing oxide removal from beneath the spacers and eliminating spacer void formation
Solution Approach 2:
The process eliminates the need for aggressive chemical cleaning by using selective epitaxial growth that naturally occurs only on exposed silicon surfaces, turning what would have been a cleaning requirement into a self-selecting growth process that inherently defines the recessed region boundaries
4Ease of manufacture
If pre-bake step is performed at high temperature before SiGe deposition, then deposition preparation is achieved, but thermal budget for implant annealing is reduced
Solution Approach 1:
The high-temperature pre-bake step is completely removed from the process sequence. The selective epitaxial growth of silicon germanium is performed at lower temperatures that do not consume the thermal budget needed for subsequent implant annealing steps, while still achieving proper deposition preparation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Preserves the integrity of the gate structure, preventing damage such as mushroom-like formation, spacer erosion, and voids, thereby enhancing transistor performance and reliability.
Implementation Method 1
a material having a different lattice constant is formed in recessed regions 20. Because the material in the recessed regions 20 have a different lattice constant, a lattice mismatch occurs and induces a strain in the region of the substrate positioned between the recessed regions 20
Implementation Method 2
A cap layer is formed over the stress-inducing material... preserving the integrity of the gate structure, preventing damage such as mushroom-like formation
Data Source
AI summary
A strained channel transistor is provided. The strained channel transistor comprises a substrate formed of a first material. A source region comprised of a second material is formed in a first recess in the substrate, and a drain region comprised of the second material is formed in a second recess in the substrate. A strained channel region formed of the first material is intermediate the source and drain region. A gate stack formed over the channel region includes a gate electrode overlying a gate dielectric. A gate spacer formed along a sidewall of the gate electrode overlies a portion of at least one of said source region and said drain region. A cap layer may be formed over the second material, and the source and drain regions may be silicided.