Strained Channel Transistor Hexagonal Recessed Trench
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Solution Overview
Problem
Existing semiconductor process technologies face misalignment issues when introducing compressive stress into N-type transistor channel regions and tensile stress into P-type transistor channel regions, affecting carrier mobility and transistor performance.
Innovation Solution
A method involving the formation of a substrate with a sacrificial gate, spacers, and a stop layer, followed by etching to create a hexagonal recessed trench for a stress-inducing material layer, allowing for epitaxial growth of a channel layer and precise stress introduction without misalignment, using a combination of anisotropic and wet etching processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If prior art techniques are used to introduce stress in channel regions, then stress can be introduced to improve carrier mobility, but misalignment problems occur affecting manufacturing precision
Solution Approach 1:
A stress inducing material layer is introduced as an intermediary element between the substrate and the channel layer. This layer is specifically positioned in a recessed trench region, acting as a mediator to transmit stress to the channel without requiring direct alignment between stress application structures and the channel, thereby solving the misalignment problem while maintaining stress-induced carrier mobility enhancement
Solution Approach 2:
The recessed trench is formed in advance before the channel layer is deposited. By pre-forming the trench and filling it with stress inducing material, the stress application geometry is established beforehand, ensuring that when the channel layer is grown epitaxially on top, the stress is automatically aligned with the channel region without requiring precise alignment during subsequent processing steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively introduces compressive stress in N-type and tensile stress in P-type transistors, enhancing carrier mobility and transistor performance by ensuring accurate stress alignment and epitaxial growth of channel layers.
Implementation Method 1
A channel layer is epitaxially grown on the stress inducing material layer
Data Source
AI summary
A method of forming a semiconductor structure. A first sacrificial gate is formed on a substrate. A spacer is formed on a sidewall of the first sacrificial gate. In the substrate, adjacent to the first sacrificial gate, a source region and a drain region are formed. A channel region is formed between the source region and the drain region. The first sacrificial gate is removed, and a gate trench is formed on the channel region between the spacers. The substrate is etched via the gate trench, thereby forming a recessed trench between the source region and the drain region, and extending into the substrate. The recessed trench has a hexagonal cross-sectional profile. A stress inducing material layer is then formed in the recessed trench. A channel layer is epitaxially grown on the stress inducing material layer. A gate structure is formed on the channel layer.