Strained Channel Transistor Fabrication via Uninterrupted Etch
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Solution Overview
Problem
Existing semiconductor transistor structures face challenges in achieving high strain in channel regions due to difficulties in forming stressor regions close to the channel, reproducibility issues with isotropic etching, and the complexity of multiple process steps required for fabrication.
Innovation Solution
A method for forming a strained channel transistor structure by creating deep source and drain stressor recesses and extension recesses through an uninterrupted etch process, followed by selective epitaxial growth of stressors, which allows for highly abrupt junctions and improved strain distribution, reducing the number of process steps and increasing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stress or pressure
If multiple process steps are used to form stressor regions close to the channel, then strain levels in the channel region can be increased, but the fabrication process complexity and manufacturing cost increase
Solution Approach 1:
The patent combines the formation of deep source/drain stressor recesses and extension recesses into a single uninterrupted etch process, eliminating the need for separate etching steps and intermediate cleaning operations. This merging of process steps reduces fabrication complexity while maintaining the ability to form stressor regions close to the channel for high strain levels.
Solution Approach 2:
The methodology performs preliminary actions by forming both the deep stressor recesses and extension recesses simultaneously in a single etch process before stressor material deposition. This preliminary formation of all necessary recess structures eliminates subsequent etching steps and reduces overall process complexity.
2Ease of manufacture
If isotropic etching is used to form stressor regions, then the etching process is simpler, but reproducibility issues occur
Solution Approach 1:
The patent introduces spacer structures as intermediary elements that define the boundaries of the extension recesses. These spacers act as precise masks during the uninterrupted etch process, ensuring reproducible formation of stressor regions close to the channel while maintaining process simplicity. The spacers mediate between the simple isotropic etching and the precise dimensional control required.
3Stress or pressure
If deep source and drain stressor recesses are formed close to the channel, then strain in the channel region is improved, but the risk of damaging the channel region increases
Solution Approach 1:
The patent uses spacer structures as intermediary protective elements that precisely define the boundary between the extension recesses and the channel region. During the uninterrupted etch process, these spacers protect the channel region from damage while allowing the extension recesses to be formed as close as possible to the channel, maximizing strain without causing harm.
Solution Approach 2:
The methodology applies local quality by forming extension recesses only in specific locations adjacent to the channel region, with precise depth control. The uninterrupted etch process creates recesses with controlled dimensions that provide high strain locally near the channel while maintaining channel integrity through precise spatial and dimensional control.
4Manufacturing precision
If separate etching steps are used for deep stressor recesses and extension recesses, then each recess can be optimized independently, but the number of process steps increases
Solution Approach 1:
The patent merges the formation of deep source/drain stressor recesses and extension recesses into a single uninterrupted etch process. The etch parameters are optimized to simultaneously create both recess types with appropriate dimensions, eliminating multiple etching steps and intermediate cleaning operations, thereby improving productivity while maintaining manufacturing precision.
Solution Approach 2:
The methodology uses parameter changes in the uninterrupted etch process to achieve independent optimization of different recess dimensions. By controlling etch time, power, gas flow rates, and chemical composition, the process can selectively etch to different depths in different regions, creating both deep stressor recesses and shallower extension recesses in a single step with optimized dimensions for each.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables higher strain levels in the channel region, improved short channel behavior, and reduced manufacturing costs by simplifying the fabrication process while maintaining high device performance.
Implementation Method 1
selective epitaxial growth of stressors
Data Source
AI summary
The present invention relates to semiconductor integrated circuits. More particularly, but not exclusively, the invention relates to strained channel complimentary metal oxide semiconductor (CMOS) transistor structures and fabrication methods thereof. There is provided a method of forming a strained channel transistor structure on a substrate, comprising the steps of: forming a source stressor recess comprising a deep source recess and a source extension recess; forming a drain stressor recess comprising a deep drain recess and a drain extension recess; and subsequently forming a source stressor in said source stressor recess and a drain stressor in said drain stressor recess. The deep source/drain and source/drain extension stressors are formed by an uninterrupted etch process and an uninterrupted epitaxy process.