Strained CMOS Transistor Structure With Buried Isolation
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Solution Overview
Problem
The miniaturization of CMOS transistor structures leads to issues such as short channel effect (SCE) and latch-up, limiting further scaling and compromising the reliability of CMOS circuits, as excessive channel length and isolation width are required to mitigate these issues.
Innovation Solution
A transistor structure is developed with a gate structure, source/drain structures, buried isolation structures, and strained etching stop layers with tensile or compressive stressors, which are formed using a method involving trench isolation, gate spacers, and localized isolation layers to accurately define the channel length and reduce latch-up paths without increasing lateral spacing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the channel length and isolation width are increased to minimize short channel effect and latch-up, then the reliability of CMOS circuit is improved, but the integration density and scaling capability are limited
Solution Approach 1:
The patent introduces buried isolation structures that extend vertically along the bottom sides of source/drain structures, transitioning from planar isolation to three-dimensional isolation. This vertical extension effectively increases the isolation width without increasing the lateral footprint, thereby improving reliability against latch-up while maintaining high integration density.
Solution Approach 2:
The isolation structure is segmented into multiple components: trench isolation structures for lateral isolation, and buried isolation structures extending vertically along source/drain regions. This segmentation allows independent optimization of each isolation component, enabling effective latch-up prevention through enhanced isolation without compromising area efficiency.
2Reliability
If the channel length is increased to minimize short channel effect, then the reliability is improved, but the switching speed is reduced
Solution Approach 1:
The patent employs vertical extension of buried isolation structures to enhance gate control over the channel. By extending isolation structures downward along the source/drain regions, the gate's electrostatic control is improved without increasing the horizontal channel length, thereby maintaining high switching speed while preventing short channel effects.
3Reliability
If the isolation width is increased to reduce latch-up paths, then the reliability is improved, but the lateral spacing between devices is increased
Solution Approach 1:
The patent transitions from lateral isolation to vertical isolation by extending buried isolation structures downward along the bottom sides of source/drain structures. This vertical positioning provides effective isolation against latch-up currents without increasing the lateral spacing between adjacent devices, thereby maintaining high integration density while improving reliability.
Solution Approach 2:
The buried isolation structures act as intermediary elements positioned vertically between the source/drain structures and the substrate. These intermediate isolation regions effectively block latch-up current paths without requiring increased lateral separation, enabling reliable operation in densely integrated circuits.
4Reliability
If trench isolation structures are formed to isolate active regions, then the latch-up is reduced, but the manufacturing complexity is increased
Solution Approach 1:
The patent combines trench isolation structures with buried isolation structures into an integrated isolation system. The buried isolation structures are formed in conjunction with source/drain fabrication steps, merging the isolation formation process with existing manufacturing flows, thereby reducing overall manufacturing complexity while achieving effective latch-up prevention.
Solution Approach 2:
The buried isolation structures are formed preliminarily during the source/drain fabrication process, before final device assembly. By establishing the vertical isolation structures early in the manufacturing sequence, subsequent processing steps are simplified, and the overall manufacturing complexity is reduced compared to forming isolation structures as separate later-stage operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for further scaling of CMOS circuits while enhancing operation speed by accurately defining channel length and reducing latch-up, without the need for excessive channel length or isolation width, thereby improving the reliability and performance of MOSFETs.
Implementation Method 1
a first strained etching stop layer covering the first source/drain structures, the first gate spacers and the first gate structure, and formed with tensile or compressive stressors
Data Source
AI summary
A transistor structure and a formation method thereof are provided. The transistor structure includes a transistor device, formed on an active region of a semiconductor substrate, and including: a gate structure, disposed on the active region; gate spacers, formed along opposite sidewalls of the gate structure; source/drain structures, formed in recesses of the active region at opposite sides of the gate structure; and buried isolation structures, separately extending along bottom sides of the source/drain structures. Further, a channel portion of the active region between the source/drain structures is strained as a result of a strained etching stop layer lying above or dislocation stressors formed in the source/drain structures.